1,079 research outputs found
Multinomial based memristor modelling methodology for simulations and analysis
No full textIn this article, we propose a novel memristor modelling methodology with multinomial window function obtained by extensive statistical fitting of the measured data of a practical memristor device. Due to such modelling, the desired electrical characteristics that a fabricated memristor device typically exhibits is accurately described. Moreover, the model features the non-linear state transition behaviour. To demonstrate the effectiveness of the proposed modelling methodology, a Verilog-A-based memristor model has been implemented, leading to further development of a memristor-based complementary resistive switch (CRS). We show that the proposed memristor modelling methodology facilitates accurate device-level characteristics and also advances effective circuits and system simulations using memristors
Introduction to energy efficient fault tolerant systems
No full textEmbedded systems are making their way into more and more devices, from hand-held gadgets to household appliances, and from mobile devices to cars. The current trend is that this growth will continue and the market is expected to experience a three-fold rise in the demand from 2013 to 2018 [20]. This growth has been possible due to continued technological advancements in terms of device miniaturization, feature richness, design cost control and performance improvement, originally described by the Moore's Law [32].</p
Author, Geraldine Brooks at the National Library of Australia for the 2009 Ray Mathew Lecture, Canberra, 23 October 2009 [picture] /
No full textTitle from acquisitions documentation.; Part of the collection: Portraits of author, Geraldine Brooks during her visit to the National Library of Australia for the 2009 Ray Mathew Lecture, Canberra, 23 October 2009.; Acquired in digital format; access copy available online.; Mode of access: Internet via World Wide Web.; Photographed by a staff member of the National Library of Australia
A unified design methodology for secure test and IP core protection
No full textOn-chip security is an emerging challenge in the design of embedded systems with intellectual property (IP) cores. Traditionally this challenge is addressed using ad hoc design techniques with separate design objectives of secure design for testability (DfT), and IP core protection. However, in this paper, we will argue that such design approaches can incur high costs. Underpinning this argument, we propose a novel design methodology, called Secure TEst and IP core Protection (STEP), which aims to address the joint objective of IP core protection and secure testing. To ensure that this objective is achieved at a low cost, the STEP design methodology employs common key integrated hardware. This hardware is incorporated in the system through an automated design conversion technique, which can be easily merged into the electronic design automation (EDA) tool chain. We evaluate the effectiveness of our proposed design methodology considering various implementations of advanced encryption standard (AES) systems as case studies. We show that our proposed design methodology benefits from design automation with high security, and protection at the cost of low area, and power consumption overheads, when compared with traditional design methodologies
Fault tolerant high performance Galios field arithmetic processor
No full textReliability is an emerging design requirement for finite field processors used in cryptographic systems. However, reliable design of these systems is particularly challenging due to conflicting design requirements, including high performance and low power consumption. In this paper, we propose a novel design technique for reliable and low power Galois field (GF) arithmetic processor. The aim is to tolerate faults in the GF processor during on-line computation at reduced system costs, while maintaining high performance. The reduction in system costs is achieved through multiple parity prediction and comparison considering the trade-offs between performance and complexity. The effectiveness of the proposed technique is then validated using a case study of 163-bit digit serial multipliers using 90nm and 180nm technology nodes highlighting the resulting area, latency and power overheads. We show that up to 40 stuck-at faults can be tolerated during computation with reasonable system area and power costs
STEP: a unified design methodology for secure test and IP core protection
No full textIntellectual property (IP) core based embedded systems design is a pervasive practice in the semiconductor industry due to shorter time-to-market and tougher cost competitions. Protecting the design information in these IP cores and securing test from various attacks are two emerging challenges in today's embedded systems design. Recently reported techniques address these challenges considering secure test and IP core protection separately. However, for ensuring high security during IP core functionality and also during test, joint consideration of secure test and IP core protection is much needed. In this paper, we propose a novel and unified design methodology, called STEP (Secure TEst and IP core Protection), which addresses the joint objective of secure test and IP core protection. The aim of STEP design methodology is to achieve high security at low system cost using the same key integrated hardware during test and IP core functionality. We evaluate the effectiveness of STEP design methodology considering advanced encryption standard (AES) system as a case study. We show that proposed design methodology benefits from high security and test accuracy, requiring up to 9% higher area and 20% power overhead
A fast and effective DFT for test and diagnosis of power switches in SoCs
No full textPower switches are increasingly becoming dominant leakage power reduction technique for sub-100nm CMOS technologies. Hence, fast and effective DFT solution for test and diagnosis of power switches is much needed to facilitate faster identification of potential faults and their locations. In this paper, we present a novel, coarse-grain DFT solution enabling divide and conquer based test and diagnosis solution of power switches. The proposed solution benefits from exponential time savings compared to previously reported solutions. Our DFT solution requires only (2Γlog2mΓ+ 3) clock cycles in the worst case for test and diagnosis for m-segment power switches. These time savings are further substantiated by effective discharge circuit design, which eliminates the possibility of false test and hence significantly reducing the charge and discharge times. We validated the effectiveness of our proposed solution through SPICE simulations on a number of ISCAS benchmark circuits, synthesized using 90nm gate libraries
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