1,967 research outputs found
Involvement of hydrogen peroxide and nitric oxide in expression of the ipomoelin gene from sweet potato.
No full textBook Discussion : PJ Powers
No full textThe UJ Campus Health Services and the Student Affairs Division in partnership with the UJ Library invite you to meet PJ Powers (Thandeka) the co-author of the book HERE I AM About the book: Here I Am, written with Marianne Thamm, is an intimate and hilarious account of the life and times of one of this country’s most recognisable and enduring performers. From the dizzying heights of international stardom to the dark depths of her struggle with alcohol, this is a must-read to explore the heady mix of politics and music of the time. More than just a story about the personal journey of one of South Africa’s most beloved music icons, this extraordinary memoir of PJ Powers – or Thandeka, as she was affectionately renamed by Soweto crowds – is set against the turbulent backdrop of South Africa’s recent political history. It features a gallery of political leaders and international celebrities, including the likes of Nelson Mandela, Graça Machel, Chris Hani, Joaquim Chissano, Queen Elizabeth II, Brenda Fassie, Sharon Stone and Robert De Niro. Facilitator: Prof Alban Burke, Director – PsyCad, University of Johannesburg PJ Powers will also perform a few songs on the day. Date: 27 August 2015 Time: 16:30 for 17:00 Venue: Auditorium (6th Floor), APK Library, University of Johannesburg (corner Kingsway and University Road, Auckland Park) RSVP: By Wednesday, 26 August 2015 to Theodorah Modise on [email protected] / 011 559 226
Book Discussion : PJ Powers
No full textThe UJ Campus Health Services and the Student Affairs Division in partnership with the UJ Library invite you to meet PJ Powers (Thandeka) the co-author of the book HERE I AM About the book: Here I Am, written with Marianne Thamm, is an intimate and hilarious account of the life and times of one of this country’s most recognisable and enduring performers. From the dizzying heights of international stardom to the dark depths of her struggle with alcohol, this is a must-read to explore the heady mix of politics and music of the time. More than just a story about the personal journey of one of South Africa’s most beloved music icons, this extraordinary memoir of PJ Powers – or Thandeka, as she was affectionately renamed by Soweto crowds – is set against the turbulent backdrop of South Africa’s recent political history. It features a gallery of political leaders and international celebrities, including the likes of Nelson Mandela, Graça Machel, Chris Hani, Joaquim Chissano, Queen Elizabeth II, Brenda Fassie, Sharon Stone and Robert De Niro. Facilitator: Prof Alban Burke, Director – PsyCad, University of Johannesburg PJ Powers will also perform a few songs on the day. Date: 27 August 2015 Time: 16:30 for 17:00 Venue: Auditorium (6th Floor), APK Library, University of Johannesburg (corner Kingsway and University Road, Auckland Park) RSVP: By Wednesday, 26 August 2015 to Theodorah Modise on [email protected] / 011 559 226
Technologically mediated learning: The future of training in Australia
No full textHosie, PJ ORCiD: 0000-0003-2585-024XFollowing a review of the economic imperatives currently facing Australia,
the future directions training will take are examined. Related training issues are considered; such as multiskilling, on-the-job training and legal issues. The author predicts that technologically mediated learning (TML),
especially interactive multimedia, will gain ascendancy as the predominant mode of delivery for training
A 0.7-V 0.43-pJ/cycle Wakeup Timer based on a Bang-bang Digital-Intensive frequency-Locked-Loop for IoT Applications
No full textA 40-nm CMOS wakeup timer employing a bang-bang digital-intensive frequency-locked loop for Internet-of-Things applications is presented. A self-biased ΣΔ digitally controlled oscillator (DCO) is locked to an RC time constant via a single-bit chopped comparator and a digital loop filter. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm 2 ). Most circuitry operates at 32× lower frequency than the DCO in order to reduce the total power consumption down to 181 nW. High frequency accuracy and a 10× enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of ΣΔ modulation to improve the DCO resolution. The proposed timer achieves the best energy efficiency (0.43 pJ/cycle at 417 kHz) over prior art while keeping excellent on-par long-term stability (Allan deviation floor <;20 ppm) and temperature stability (106 ppm/°C).Accepted Author Manuscript(OLD)Applied Quantum Architecture
EFEKTIVITAS PASAL 1 PERATURAN DIREKTUR JENDRAL PAJAK NOMOR PER-18/PJ/2017
Full text linkTahap Penelitian atau yang penulis biasa sebut dengan validasi SSP (Surat Setoran Pajak) merupakan tahap final dimana seorang wajib pajak telah melakukan kewajibannya dalam penyetoran pajak, dan dalam proses validasi itu sendiri tidak semua akan diterima oleh kantor pajak setempat karena masih akan dilakukan penelitian baik penelitian serara formil maupun materiil. Untuk mekanismenya validasi telah ditetapkan dalam Per-18/Pj/2017 Tentang Cara Penelitian Bukti Pemenuhan Kewajiban Penyetoran Pajak Penghasilan Atas Penghasilan Dari Pengalihan Hak Atas Tanah Dan/Atau Bangunan, Dan Perjanjian Pengikatan Jual Beli Atas Tanah Dan/Atau Bangunan Beserta Perubahannya. Efektifitas pasal 1 Peraturan Direktur Jendral Pajak Nomor Per-18/Pj/2017 di Kantor Pajak Pratama Kota Malang telah sesuai akan tetapi untuk pasal 1 ayat 2 masih belum dan untuk pengikatan jual beli, dan mengenai cara pembuktian bahwa wajib pajak telah memenuhi kewajiban penyetoran adalah dengan cara validasi ataupun telah di telitiKata Kunci: kewajiban, penyetoran, pemenuhan, pajak, validasiThe Research Phase or what the author commonly refers to as SSP validation (Tax Payment Deposit) is the final stage in which a taxpayer has carried out his obligations in tax payments, and in the process of validation itself not all will be accepted by the local tax office because there will still be done a research both formal and material. For the mechanism of validation, it has been stipulated in Per-18 / Pj / 2017 Regarding the Method of Research of Evidence of Fulfillment of Obligation of Income Tax on Income from Transfer of Land and / or Building Rights, and Agreement on Binding of Sale and Purchase of Land and / or Buildings and Amendments. The effectiveness of article 1 of the Regulation of the Director General of Tax Number Per-18 / Pj / 2017 in the Pratama Tax Office Malang is appropriate but for article 1 paragraph 2 it is still not yet for the binding of buying and selling, and regarding the means of proving that the taxpayer has fulfilled the payment obligation is by validation or thoroughlyKeywords: oblilgation, deposit, fulfillment, tax, validatio
A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS
No full textWe present a wireline transmitter (TX) for re-configurable chip-to-chip links. The proposed design features a frequency-adaptive clock chain, a fast 16:1 clocked-CMOS multiplexer (C2MOS MUX) tree, and a full-rate synchronous current-mode logic (CML) clock driver. A prototype realized in 40-nm CMOS accomplishes a wide 0.1-to-11 Gb/s operation range (fmax/fmin = 110×). At 11 Gb/s, the prototype achieves 3.98 pJ/bit for a bit error rate (BER) < 10-12 with a 60.9-ps eye width.Accepted author manuscriptElectronic
A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs
No full textUltra-low voltage operation is key to achieving energy-efficient operation for microcontroller (MCU) systems. Variation resiliency, high speed operation, and short design time are the most important challenges for these systems. This paper overcomes these challenges in a new design strategy that enables standard cell design with differential transmission gate logic. The commercial toolchain is extended with in-house developed add-ons and makes use of two custom libraries with different device lengths to allow high speed vs. low leakage trade-offs. The design flow is used to prototype two highly efficient 32-bit ARM Cortex-M0 MCU systems in 40-nm CMOS. The core of the first prototype scales down to 190 mV and 0.8-MHz and reaches 16.07 pJ/cycle at 31.2-MHz and 440 mV. The second prototype benefits from the dual libraries and reduces core energy consumption by 50% at the same speed performance. Minimum energy operation is thus achieved at an even lower voltage (370 mV) with the M0 core consuming only 8.80 pJ/cycle at 13.7-MHz, breaking the sub-10-pJ/cycle barrier for a 6–35-MHz range.sponsorship: This paper was approved by Guest Editor Eugenio Cantatore. This work was supported by the IWT-Agency for Innovation by Science and Technology. (Corresponding author: Hans Reyserhove.) (IWT-Agency for Innovation by Science and Technology)status: Publishe
Illustrative example of COI relationship between different authors.
No full textWhere Pn and Am are the list of articles and authors respectively, red dashed line indicates citing relationship. The figure shows two cases: (1) Before Pi cites Pj, the author(s) of Pi has (have) collaborated with the author(s) of Pj, just like P2 cites P1, Author A1 and Author A3 co-author P5, Author A1 and Author A4 co-author P6, that is to say, there are two co-author pairs (A1, A3), (A1, A4); (2) Before Pi cites Pj, the author(s) of Pi has (have) not collaborated with the author(s) of Pj, just like P3 cites P2, however, if author A3 and author A5 belong to the same affiliation, (A3, A5) composes suspect COI author pair.</p
A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology
No full textThis paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under -6dB channel loss at 50GHz. Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Electronic Instrumentatio
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