20 research outputs found
Hyojun dai toa bunzu. 18 , Hawai shoto hen /
No full textMap of Hawaii published in Japan in 1943.; Also available in an electronic version via the internet at: http://nla.gov.au/nla.map-vn6451628. 880-04 Inset: Shinjuwan oyobi Honoruru fukin -- Hawai shoto fukin (Sandoicchi shoto). Scale 1:9,000,000.880-04 Inset: 1-MO!KB'IC!5#i%[i%Ni%ki%k!0o
No full textNext-generation artificial tactile systems demand seamless integration with neuromorphic architectures to support on-edge computation and high-fidelity sensory signal processing. Despite significant advancements, current research remains predominantly focused on optimizing individual sensor elements, and systems utilizing single neuromorphic components encounter inherent limitations in enhancing overall functionality. Here, we present a vertically integrated in-sensor processing platform, which combines a three-dimensional antiferroelectric field-effect transistor (AFEFET) device with an aluminum nitride (AlN) piezoelectric sensor. This innovative architecture leverages a Zr-rich, leaky antiferroelectric HZO film-a novel material for physical reservoir computing (PRC) devices capable of responding to external stimuli within the microsecond-to-millisecond range. We further demonstrate the 3D AFEFET's adaptability by tuning its discharge current via structural modifications, enabling sophisticated multilayered processing. As an integrated in-sensor processing unit, the 3D AFEFET and AlN sensor array surpass a comparable 2D configuration in both pattern recognition and information density. Our findings showcase a pioneering prototype for future artificial tactile systems, demonstrating the transformative potential of 3D AFEFET PRC devices for advanced neuromorphic applications.
Experimental Analysis and Mathematical Modeling of Program Efficiency in Gate-Side Injection Type FeFETs Depending on the Gate Interlayer
No full textWe experimentally analyze the incremental step pulse programming (ISPP) characteristics of gate-side injection type MIFIS FeFETs, which feature a metal - gate interlayer (G.IL) - ferroelectrics - channel interlayer (Ch.IL) - Si stack, with a focus on the role of the G.IL. We also propose a mathematical model considering ferroelectric (FE) switching behavior. MIFIS FeFETs have recently garnered attention due to their ability to achieve lower program (PGM) voltages and wider memory windows (MWs) compared to typical channel-side injection type charge trap flash (CTF) devices, thanks to the injection of charges (Q(it)') from the gate and polarization switching dynamics. However, guidelines on the influence of the G.IL on ISPP characteristics and endurance, critical for NAND cell, are lacking. Here, we experimentally investigate the impact of the G.IL on the ISPP slope of MIFIS FeFETs and, through mathematical modeling, propose a G.IL design to optimize MIFIS FeFET performance. Furthermore, we analyze the degradation of endurance characteristics depending on the type of G.IL, suggesting that the excessive Q(it) injected from the Ch.IL, together with polarization pinning, contributes to overall endurance degradation. Lastly, we demonstrate that by utilizing a low-kappa SiO2 G.IL (6 nm), a MW of 6.5 V and an ISPP slope greater than 3 can be achieved. Our MIFIS FeFET also exhibits disturbance immunity even at voltages exceeding 14 V, which is critical in preventing V-th shifts during various disturbances. Our research and model can provide valuable guidelines for the study of gate-injection type FeFET, which are actively being explored as next-generation NAND Flash memory technologies.
비휘발성 메모리향 하프니아 강유전체 트랜지스터 설계
No full text학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2025.2,[iii, 32 p. :]To enhance the integration density of 3D NAND flash memory, vertical 3D stacking structures have been introduced, with the number of stacked layers increasing with each new generation of devices. The adoption of charge trap flash technology and various 3D integration techniques has driven remarkable scaling advancements. Future projections indicate that the number of stacked layers could surpass 500 and potentially reach 1000. While increasing the number of stacked layers proportionally enhances storage capacity, it necessitates the formation of high-aspect-ratio channel holes. This high-aspect-ratio etching process introduces significant challenges, as the increased mold height raises the complexity of manufacturing processes.
To address these challenges, two primary approaches have been proposed: reducing the word line pitch and increasing the information storage capacity per bit. However, reducing the word line pitch often results in reliability issues due to the reduced breakdown voltage of the dielectric spacer, while increasing the storage capacity per bit requires higher operating voltages to achieve a sufficient memory window. The primary scaling challenge currently facing 3D NAND flash memory is the high operating voltage, which hinders further advancements. To overcome this limitation, research is being conducted on non-volatile memory utilizing ferroelectric transistors, which leverage the spontaneous polarization, low operating voltage, and high dielectric constant properties of ferroelectric materials.
This thesis proposes two methodologies to optimize ferroelectric transistors. First, it evaluates the memory characteristics of ferroelectric transistors with a Metal-Ferroelectric-Interlayer-Silicon (MFIS) structure by varying the thickness of the interlayer (Ch.IL) on the channel side. Second, it examines the memory characteristics of ferroelectric transistors with a Metal-Interlayer-Ferroelectric-Interlayer-Silicon (MIFIS) structure by analyzing the effects of the interlayer thickness (G.IL) on the gate side and its electrical properties. Based on the findings of these studies, design guidelines for ferroelectric transistors are proposed to enhance their performance and reliability.한국과학기술원 :전기및전자공학부
Middle Interlayer Engineered Ferroelectric NAND Flash Overcoming Reliability and Stability Bottlenecks for Next-Generation High-Density Storage Systems
No full textMultilevel storage and low-voltage operation position ferroelectric transistors as promising candidates for next-generation nonvolatile memory. Among them, gate-injection-type ferroelectric transistors offer improved vertical scalability and power efficiency for three-dimensional (3D) NAND flash. However, their intricate interplay between polarization switching and charge trapping complicates systematic understanding of degradation mechanisms, limiting strategies to improve reliability and stability. Here, gate stack engineering incorporating middle interlayers within HfZrOx matrix is presented to modulate polarization dynamics, strengthening the coupling of dual mechanisms and overcoming long-standing reliability and stability bottlenecks in ferroelectric NAND operation. This approach achieves a memory window up to 11 V, an operating voltage below 18 V, triple-level-cell retention beyond 10 years, disturbance immunity, and 54% reduced threshold voltage variability. A 20% reduction in program voltage compared to conventional NAND enables aggressive vertical scaling, leading to 25% higher bit-density. Furthermore, analytical modeling provides insights into gate stack optimization. These findings establish ferroelectric NAND as a scalable, energy-efficient solution for next-generation storage.
Study concerning Transcription of Staff Notation for Tokiwazubushi by Hogaku Chosa-gakari
No full textIn the study of tokiwazubushi, progress has been made in the historical study of its performances and performers, but little has been done from the point of view of music. The author thinks that one large factor for this is that there is no “score” in tokiwazubushi that can be considered as a common language. For example, of the officiall １y published scores 6 (of these 2 are only small parts of repertoire) from Hogakusha are in the style of bunkafu notation while 1 from Tokiwazu Hyojun-fuhon Kanko-kai is in the style of kenseikaifu notation. Such circumstance not only makes the musical study of tokiwazubushi difficult but also casts a shade on the promotion and transmission of tokiwazubushi.
Fear toward such a situation already existed in the Taisho period. Hogaku Chosa-gakari, an official group involved in the investigation of Japanese music established within the music department of the Imperial Household Ministry (1907-1943 ?) attempted to write tokiwazubushi score on the staff notation system. The present paper clarifies the purpose, history and method of that attempt based on material from the archives of the Tokyo University of Arts to consider the significance and issues related to the attempt to write tokiwazubushi scores on staff notation system.
This paper is a part of the results obtained from the project of “Grants-in Aid for Scientific Research from the Japan Society for the Promotion of Science (C), ‘Fundamental research for musical analysis of tokiwazubushi (18K00158, Maehara Megumi).departmental bulletin pape
Enhancement of electrical properties of morphotropic phase boundary in Hf1-xZrxO2 films by integrating Mo electrode and TiN interlayer for DRAM capacitors
No full textMolybdenum is considered a promising electrode material for Hf1-xZrxO2 films owing to its enhancing impact on ferroelectricity and dielectric constant. However, it poses significant limitations, such as high leakage current density and low endurance, which must be addressed to ensure its applicability in Hf1-xZrxO2-based memories. The insertion of a TiN interlayer has been proven to effectively reduce the oxidation of a Mo electrode and suppress the formation of oxygen vacancies in Hf1-xZrxO2 films, as confirmed by transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) studies. An optimized 6 nm-thick Hf0.3Zr0.7O2 film with a TiN interlayer exhibited a leakage current density below 10–7 A/cm² at 0.8 V and an equivalent oxide thickness of 0.49 nm, demonstrating its suitability for cell capacitors in dynamic random-access-memories (DRAM)
Strategies for Reducing Operating Voltage of Ferroelectric Hafnia by Decreasing Coercive Field and Film Thickness
No full textAbstract As the AI era advances, there has been increasing interest in the next‐generation memory capable of low‐power operation as well as high performance. HfO₂‐based ferroelectric random‐access memory (FeRAM) has been extensively studied for its simple structure similar to that of dynamic random‐access memory (DRAM) and high power efficiency. However, due to the limited endurance of HfO2 and the high coercive field (Ec) arising from its high energy barrier for polarization switching, the commercialization of the low‐power FeRAM faces several challenges. To address these issues, this perspective reviews current scientific approaches and experimental advances aimed at achieving low voltage switching in ferroelectric HfO2 thin films by reducing either Ec or film thickness. Key strategies including controlling types and number of dopants in HfO2, decreasing free energy of the intermediate tetragonal phase, achieving metal‐excess rhombohedral phase, controlling oxygen vacancy concentration, and enhancing domain wall motion are reviewed based on theory as well as experimental demonstrations. Especially, recent progress in achieving low voltage operation in ferroelectric HfO2 capacitors via sub‐5 nm thickness scaling are highlighted. Overall, the importance of precise material and process control to overcome current technical limitations in device scalability and reliability is emphasized, casting an optimistic outlook on the future of ferroelectric memory technology
Detection and Accurate Classification of Mixed Gases Using Machine Learning with Impedance Data
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