1,929 research outputs found
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Enabling Heterogeneous Computing for Software Developers
No full textThe slowing of CMOS technology scaling mismatches the ever-increasing demand for computational power, leading to a rise in the use of heterogeneous systems, which pair scalar processors such as CPUs with specialized accelerators like FPGAs and GPUs. These systems enable continued performance and efficiency scaling for specialized tasks while retaining limited generality. This restricted generality inherent in heterogeneous platforms requires specialized knowledge of hardware architectures and low-level programming models, posing a substantial barrier to software developers.This dissertation addresses the challenges software developers face in leveraging heterogeneous computing resources, particularly FPGA acceleration. We identify three major limitations: limited programmability support in domain-specific resources, difficulty in achieving high performance and efficiency, and time-consuming porting across diverse computational architectures. We present novel approaches and tools to bridge the gap between high-level software development and efficient hardware implementation, making heterogeneous computing more accessible to a broader range of developers.In this dissertation, we introduce Heterosys, an end-to-end optimization framework simplifying heterogeneous hardware development. It decouples algorithmic descriptions from underlying fabrics and offers layout-driven and architecture-driven design generation, bridging the gap between high-level designs and hardware details.The frontend of Heterosys is HeteroRefactor, which combines dynamic invariant analysis, automated refactoring, and selective offloading. HeteroRefactor optimizes software kernels onto accelerators for common-case inputs while maintaining correctness through CPU fallback mechanisms. HeteroRefactor automatically refactors software code to make it FPGA-compatible and hardware-friendly, reducing chip resource usage through bitwidth optimization and floating-point precision tuning.From the individual synthesizable hardware kernels, Adroit optimizes them using a static approach to identify data and control broadcasts. It analyzes data and control dependencies in the source code and reports, trading off clock-cycle latency for higher frequency. By optimizing the FPGA architecture generated by high-level synthesis tools, Adroit relieves software developers from needing to understand the underlying fabric.As the backend, Heterosys composes multiple kernels into an optimized FPGA system using RapidIR, a comprehensive infrastructure for high-level physical synthesis optimizations. RapidIR integrates coarse-grained floorplanning with high-level pipelining, supporting hierarchical composition of heterogeneous designs from diverse sources. It automates the exploration of various physical optimization strategies, freeing programmers from designing device-specific hardware layouts for each target device.Our research demonstrates substantial performance improvements across diverse applications and benchmarks, including genomic sequencing and large language model accelerations. Our FPGA optimization techniques achieve operating frequency improvements of 30% to over 100% compared to state-of-the-art EDA tools, resource requirement reductions of 21% to over 90%, and 51% code reduction in porting between platforms.This dissertation contributes a comprehensive set of methodologies and tools that significantly lower the barriers to entry for heterogeneous computing, particularly FPGA acceleration. By abstracting away much of the hardware complexity, our work paves the way for broader adoption of heterogeneous acceleration in software development practices, potentially driving research innovation and performance improvements across a wide range of applications and industries
Shakespeare and Space
No full textCo-editor of book, with Cong Cong, and author of the chapter 'London, Stratford, Coventry: Shakespearean theatre and the spaces of history
CONG AND HWANG UCLA CSD TR-950001 Abstract Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping
No full textIn this paper, we present an improvement of the FlowMap algorithm, named CutMap, which combines depth and area minimization in the mapping process by computing min-cost min-height K-feasible cuts for nodes which are on critical paths for depth minimization and computing min-cost K-feasible cuts for nodes which are not on any critical path for area minimization. CutMap guarantees depth-optimal mapping solutions in polynomial time as the FlowMap algorithm but uses considerably fewer LUTs. We have implemented CutMap and tested it on the MCNC logic synthesis benchmarks. For depth-optimal mapping solutions, CutMap uses 20 % fewer K-LUTs than FlowMap without post-processing, and uses 13 % fewer K-LUTs than FlowMap when post-processing operations for area minimization are applied to both solutions. When targeting for Xilinx X3000 FPGA family, CutMap uses 11 % fewer CLBs than FlowMap. We also tested CutMap followed by the depth relaxation routines in FlowMap_r algorithm, which achieves area minimization by depth relaxation. CutMap followed FlowMap_r performs better than FlowMap_r. 1 CONG AND HWANG UCLA CSD TR-95000
Roundtable Panel Discussion at DAC 2019: Evolutionary Computing or Heuristic Forever?
No full textAs demands for computing have been continuously increasing, various solutions have been proposed. Some approaches deal with improving algorithms and software programs, mainly through the tuning of advanced heuristics and learning methods. Some other tackle the problem by providing specialized hardware to enhance computation. Other revolutionary approaches, such as memcomputing and quantum computing, explore new paradigms in computation to beat the barrier of computational complexity. A highly attended plenary panel at the 2019 Design Automation Conference (DAC) in Las Vegas, NV, USA, with the provocative title "Evolutionary Computing or Heuristic Forever?" spurred a lively discussion that is reported in this Roundtable. It is moderated by the panel organizer and moderator Giovanni De Micheli, EPFL, Switzerland. Panelists include Antun Domic, former CTO and senior VP at Synopsys; Jason Cong, University of California Los Angeles (UCLA); Massimiliano Di Ventra, University of California San Diego (UCSD); and Martin Roettler, Microsoft Research.LSI
Scaling Up Physical Design: Challenges and Opportunities
No full textDue to the continuous scaling of integration density and the increasing diversity of customized designs, there are increasing demands on the scalability and the customization of EDA tools and flows. Commercial EDA tools usually provide an interface of TCL scripting to extract and modify the design information for a flexible design flow. However, we observe that the current TCL scripting is not designed for the complete netlist extraction, resulting in a significant degradation in performance. For example, it takes over 20 minutes to extract the complete netlist of a 466K-cell design using TCL. This extraction may be repeated several times when interfacing between the existing EDA platforms and the actual distributed EDA algorithms. This drastic decrease in efficiency is a great barrier for customized EDA tool development. In this paper, we propose to build a distributed framework on top of TCL to accelerate the netlist extraction, and use the distribution detailed placement as an example to demonstrate its capability. This framework is promising in scaling out physical design algorithms to run on a cluster.EICPCI-S(ISTP)[email protected]; [email protected]; [email protected]; [email protected]
Doctor-family-patient relationship: The Chinese paradigm of informed consent
No full textBioethics is a subject far removed from the Chinese, even from many Chinese medical students and medical professionals. In-depth interviews with eighteen physicians, patients, and family members provided a deeper understanding of bioethical practices in contemporary China, especially with regard to the doctor-patient relationship (DPR) and informed consent. The Chinese model of doctor-family-patient relationship (DFPR), instead of DPR, is taken to reflect Chinese Confucian cultural commitments. An examination of the history of Chinese culture and the profession of medicine in China is used to disclose the deep roots of these commitments. The author predicts that the DFPR model will further develop in China but that it will maintain its Chinese character.EthicsSocial Sciences, BiomedicalPubMedCPCI-SSH(ISSHP)SSCI4
Innovative Structure Solution for Discharge Sluice at Vung Tau Go Cong Viet Nam
No full textThe demand for large discharge sluices in Viet Nam is increasing as the constructions of small river barriers show their restrictions in flooding and salt intrusion protection. The main objective of this study is therefore to research an appropriate design for the sluice structure type that can be applied in Vung Tau Go Cong, which is the largest project of discharge sluice in Viet Nam so far. From the literature review, it can be seen that in the Netherlands, several units of sluice caisson have been applied but their main function was only to permanently close the basin, while in Viet Nam only a single caisson is applied as small river barriers. It is to say that a large discharge sluice with several units of caisson has never been built so far. In contrast with this type of structure, most of discharge sluices and barriers in the world have been build according to the “pier structure type”. In the Netherlands piers and bottom slabs are normally placed on batter pile foundations. Meanwhile in Viet Nam, piers are often placed on vertical pile foundations and a bottom slab is replaced by supporting beams. Because of both “proven structure”- caisson and pier have their own strong and weak points, by combining the best features of these “proven technologies” of the Netherlands and Viet Nam; two appropriate structure types were designed and the critical concerns related to them were checked. It is concluded that the caisson and pier sluice structure are feasible solutions for the discharge sluice at Vung Tau Go cong. It can be also considered as an innovative structure for larger discharge sluice.Coastal and Marine Engineering and Management (CoMEM)Hydraulic EngineeringCivil Engineering and Geoscience
Theory and Algorithm of Local-Refinement-Based Optimization with Application to Device and Interconnect Sizing
No full textIn this paper we formulate three classes of optimization problems: the simple, monotonically constrained, and bounded Cong-He (CH)-programs. We reveal the dominance property under the local refinement (LR) operation for the simple CH-program, as well as the general dominance property under the pseudo-LR operation for the monotonically constrained CH-program and the extended-LR operation for the bounded CH-program. These properties enable a very efficient polynomial-time algorithm, using different types of LR operations to compute tight lower and upper bounds of the exact solution to any CH-program. We show that the algorithm is capable of solving many layout optimization problems in deep submicron iterative circuit and/or high-performance multichip module (MCM) and printed circuit board (PCB) designs. In particular, we apply the algorithm to the simultaneous transistor and interconnect sizing problem, and to the global interconnect sizing and spacing problem considering the coupling cap..
Inter-Device Communication in Near Storage Computation
No full textNear storage computation has increasingly become a focus in improving the performance of big data systems. Technological trends have moved the bottle neck of data intensive workloads to the interconnects used to move data from storage to memory. This has given a rise to the need for moving processing power closer to where the data is stored. The solution presented in this paper aims to provide a developer friendly approach to computational storage that allows multiple computational storage capable devices to be used effectively by enabling data transfer between computational storage devices directly. In this work, we build a model system on Amazon AWS and run a merge sort workload to evaluate the benefits of allowing device to device communication. We identify the scenarios in which device to device communication is effective and propose additional optimizations and improvements to better the overall solution
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Coprocessor Acceleration for Domain-Specific Computing
No full textThere is a growing trend to use coprocessors to offload and accelerate domain-specific applications in order to obtain significant performance improvement and energy/power reductions. Two important coprocessor components in the heterogeneous system are the GPU and FPGA. GPU (graphics processing unit) is increasingly used as a data-parallel coprocessor for general computations. The newest GPU has a much larger number of cores (compared to CPU) and very high peak FLOPS. FPGA (field programmable gate array), on the other hand, allows users to customize, at fine-grain level, the computational data path and memory hierarchy according to the exact need of the applications. FPGA excels in integer operations and bit-level operations. The thesis starts with several coprocessor acceleration examples for our focus application domains: the first domain is on VLSICAD algorithms and the second is on computational medical imaging. We detail application acceleration examples in the domains including lithography simulation for IC manufacturing, medical image reconstruction using compressive sensing, and medical image registration using fluid models. Both GPU-accelerated versions and FPGA-accelerated versions have been implemented. Based on these implementations, we then analyze the performance and energy trade-offs, the interaction between the diverse application requirements and a spectrum of hardware systems, and how those domain-specific coprocessor acceleration case studies further bring us insights for domain-specific architecture innovations. In the end, we showcase an example for collaborative execution on the heterogeneous platform. Different scheduling policies are needed to optimize performance or energy. The thesis concludes as we present reusable architecture templates and realizations for futuristic accelerator-rich CMPs
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