242 research outputs found
Diagnostic Test Generation for Statistical Bug Localization using Evolutionary Computation
No full textVerification is increasingly becoming a bottleneck in the process of designing electronic circuits. While there exists several verification tools that assist in detecting occurrences of design errors, or bugs, there is a lack of solutions for accurately pin-pointing the root causes of these errors. Statistical bug localization has proven to be an approach that scales up to large designs and is widely utilized both in debugging hardware and software. However, the accuracy of localization is highly dependent on the quality of the stimuli. In this paper we formulate diagnostic test set generation as a task for an evolutionary algorithm, and propose dedicated fitness functions that closely correlate with the bug localization capabilities. We perform experiments on the register-transfer level design of the Plasma microprocessor coupling an evolutionary test-pattern generator and a simulator for fitness evaluation. As a result, the diagnostic resolution of the tests is significantly improved
Ultra-low latency NoC testing via pseudo-random test pattern compaction
No full textThis paper aims at devising an optimized pseudo-random test methodology for NoCs and its architectural support. The guiding principle consists of using a test pattern compaction engine for generating minimal test lengths. We show the application of this principle driven by the objective to minimize test application time, at the cost of test wrapper complexity. The achieved design point results in a reduction of test application time by two orders of magnitude with respect to state-of-the-art test architectures for NoCs exploiting pseudo-random patterns. © 2012 IEEE
Promoting Democracy through Civil Society: How to Step up the EU’s Policy towards the Eastern Neighbourhood. CEPS Working Documents No. 237, 1 February 2006
No full textThe European Union has successfully supported democratisation in its new Eastern member states and candidate countries. Now it needs to become more engaged in those post-communist countries where democratisation is incomplete or stalled. This study argues that civil society should be a more important priority of democracy promotion in the EU’s Eastern neighbourhood and calls for a strategic and differentiated approach designed according to the stage of democratisation in the target country. The paper focuses on three countries that represent three types of cases in the eastern neighbourhood: Ukraine, which has become a ‘re-transition’ country after the Orange Revolution; Moldova, where we can observe a prolonged transition; and Belarus, an outright dictatorship. One of the well-known obstacles to enhancing the EU’s support to civil society in these countries is posed by the bureaucratic procedures of aid programmes. However, even if the rules were substantially reformed, it would still be difficult for the European Commission to work extensively with NGOs in foreign countries for political as well as institutional reasons. Hence, the EU should create new mechanisms of democracy assistance. The German and US foundations set up specifically for this purpose have proved to be a model with many advantages; similar European foundation(s) could be an invaluable tool for supporting pro-democratic forces in authoritarian countries in particular. The paper also examines two other exemplary models for the European neighbourhood policy: the Swedish practice to channel support through domestic NGOs, and the EU’s own policy, which has only been applied in candidate countries so far, to use local civil society development foundations
Mutation analysis with high-level decision diagrams
No full textThe paper presents a new tool for mutation analysis using the system model of high-level decision diagrams (HLDD). The tool is integrated into the APRICOT verification environment. It is based on HLDD simulation and graph perturbation. A strategy that relies on a restricted set of five key mutation operators is developed in order to speed up the mutation analysis. Experiments on several ITC99 benchmarks and an industrial example show the feasibility of the mutation analysis approach
Mutation Analysis for SystemC Designs at TLM
No full textMutation analysis has been borrowed from the software testing domain as a technique for evaluating the quality of testbenches in validating digital systems. This paper presents a new method for applying mutation analysis on SystemC hardware designs at Transaction-Level Modeling (TLM). The method injects mutants by directly perturbing the SystemC code. Five key categories of mutation operators are implemented in order to speed up the analysis process. In the paper, a comparison of mutation analysis at two different abstraction levels - TLM and Register-Transfer Level (RTL), is carried out. The experiments show that mutation analysis is considerably faster at TLM than it is at RTL while achieving almost equal mutant coverage. Last but not least, TLM mutation analysis provides also more readable feedback for the engineer to improve the testbench. To the best of our knowledge this is the first method for mutation analysis directly working on uncompiled SystemC TLM code
Error resilient OBDDs
No full textOrdered Binary Decision Diagrams (OBDDs) are a widely used data structure for Boolean function manipulation. In particular, OBDDs are commonly used in CAD for the synthesis and verification of integrated circuits. The purpose of this paper is to design an error resilient version of this data structure, i.e., self-repairing OBDDs.We describe some strategies that make reduced OBDDs resilient to errors in the indexes, that are associated to the input variables, or in the edges. The solutions we propose allow to efficiently restore via software the corrupt OBDD without changing the data structure, but rather exploiting its inherent redundancy, as well as the redundancy introduced by its efficient implementations
Combining Dynamic Slicing and Mutation Operators for ESL Correction
No full textVerification is increasingly becoming the bottleneck in designing digital systems. In fact, most of the verification cycle is not spent on detecting the occurrences of errors but on debugging, consisting of locating and correcting the errors. However, automated design-error debug, especially at the system-level, has received far less attention than error detection. Current paper presents an automated approach to correcting system-level designs. We propose dynamic-slicing and location-ranking-based method for accurately pinpointing the error locations combined with a dedicated set of mutation operators for automatically proposing corrections to the errors. In order to validate the approach, experiments on the Siemens benchmark set have been carried out. The experiments show that the proposed method is able to correct three times more errors compared to the state-of-the-art mutation-based correction methods while examining fewer mutants
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