29 research outputs found

    Substrate-dependent high-field transport and self-heating in graphene transistors

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    Over the last decade graphene has attracted much interest for nanoelectronic applications due to its high and symmetrical carrier mobility, and high drift velocity compared to silicon. However, when graphene is placed on insulating substrates such as SiO2 or flexible plastics, its inherent superior qualities get suppressed by the influence of the underlying substrate. Interfaces and substrate material properties have a significant impact on graphene based nano-scale devices due to the reduced dimensions and large surface-to-volume ratio. Motivated by this issue, in this work we have investigated the substrate dependence of the electrical and thermal transport in graphene field-effect transistors (GFETs). We developed a simple yet practical electro-thermal model along with extensive calibration with experimental data. Special emphasis is given to the study of high-field transport and investigation of temperature-induced effects on device performance. First, we have used this electro-thermal model to examine the scaling effect of the supporting insulator (e.g. SiO2, BN) thickness on temperature maximum (hot spot) formation. Our findings showed average and maximum temperatures of GFETs scale differently due to competing electrostatic and heat sinking effects. Self-heating in GFETs causes current degradation (up to ~10-20%) in micron-sized devices on SiO2/Si but is reduced if the supporting insulator thickness is scaled down. The transient behavior of such FETs has thermal time constants in the range of 50-250 ns, dominated by the thickness of the supporting insulator and that of device capping layers. Self-heating is also reduced in shorter channel devices, due to partial heat sinking at the contacts. Next, we investigate the effect of different supporting dielectrics such as hexagonal boron nitride (h-BN), HfO2 and SiO2 on the velocity saturation of GFETs. We examine the effects from different substrates as they each present a unique scenario due to their different (re-mote) phonons and thermal conductivities, all of which influence high-field transport in GFETs. Additionally, we studied the origins of the poor current saturation in short-channel GFETs in de-tail. We study and compare the temperature profiles generated in GFETs on different insulating materials for bottom oxide and substrate through full thermal finite element method (FEM). Ma-terials with anisotropic thermal conductivity showed significant impact in heat spreading and temperature rise in the hot-spot. We apply our findings to add a guideline for the maximum “safe” power density, e.g. in GFETs on flexible substrates such as polyimide (PI), without inducing thermal deformation; the maximum is found to be ~1.8 mW/µm2 (with 200 nm BN dielectric). Finally, we also develop a physics-based compact model based on existing literature, for GFETs with well calibration against experimental data and other finite element models. This model has been implemented into a circuit simulator like Verilog-A with a minimum number of iterations for channel potential calculation. These results shed important physical insight into the high-field and thermal profile of graphene transistors. Moreover, the electro-thermal model and results presented in this dissertation can be extended for analysis of other 2D materials beyond graphene.Item withdrawn by Mark Zulauf ([email protected]) on 2014-10-20T14:43:11Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Islam_Sharnali.pdf: 2804830 bytes, checksum: 7a4f9db23877fb5e2f7d7412ec457b9f (MD5)Made available in DSpace on 2015-01-21T19:55:10Z (GMT). No. of bitstreams: 1 Sharnali_Islam.pdf: 2804830 bytes, checksum: 7a4f9db23877fb5e2f7d7412ec457b9f (MD5)Embargo set by: Seth Robbins for item 73164 Lift date: 2017-01-21T19:56:18Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemU of I Only Restriction Lifted for Item 73164 on 2017-01-22T10:15:40Z

    ATOMISTIC MODELING OF UNINTENTIONAL SINGLE CHARGE EFFECTS IN NANOSCALE FETS

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    Numerical simulations have been performed to study the single-charge-induced ON current fluctuations (random telegraphic noise) in conventional (MOSFET) and non-conventional (silicon nanowire) nanoscale field-effect transistors. A semi-classical three-dimensional particle-based Monte Carlo device simulator (MCDS 3-D) has been integrated and used in this work. Quantum mechanical space-quantization effects have been accounted for via a parameter-free effective potential scheme that has been proved quite successful in describing charge set back from the interface and quantization of the energy (bandgap widening) within the channel region of the device. The effective potential is based on a perturbation theory around thermodynamic equilibrium and leads to a quantum field formalism in which the size of the electron depends upon its energy. To treat full Coulomb (electron-ion and electron-electron) interactions properly, the simulator implements two different real-space molecular dynamics (MD) schemes: the particle-particle-particle-mesh (P3M) method and the corrected Coulomb approach. For better accuracy, particularly in case of nanowire FETs, bandstructure parameters (bandgap, effective masses, and density of states) have been computed via a 20-band nearest-neighbor sp3d5s* tight-binding scheme. Also, since the presence of single impurities in the channel region represents a rare event in the carrier transport process, necessary event-biasing algorithms have been implemented in the simulator that, while enhancing the statistics, results in a faster convergence in the chan-nel current. The study confirms that, due to the presence of single channel charges, both the electrostatics (carrier density) and dynamics (mobility) are modified and, therefore, simultaneously play important roles in determining the magnitude of the current fluctuations. The relative impact (percentage change in the ON current) depends on an intricate interplay of device size, geometry, crystal direction, gate bias, temperature, and energetics and spatial location of the trap

    Numerical Simulation of Highly Efficient Lead-free MAGeI3 Based Perovskite Solar Cell for Various ETL and HTL Layers

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    The eco-friendly and highly stable lead-free MAGeI_3 perovskite solar cell has proved itself as a potential candidate for conventional lead-based perovskite solar cells with high efficiency. In this paper, numerical simulation has been performed over MAGeI_3 solar cell with three different Electron Transport Layer (ETL) and Hole Transport Layer (HTL) materials to obtain the best combination of ETL/perovskite/HTL layers using the solar cell simulation tool SCAPS-1D. The best performance has been found for the ITO/ZnO/MAGeI_3/NiO_x structure with an efficiency of 21.19% (V_ of 1.89 V, J_ of 16.11 mA/cm^2, and FF of 69.57%) due to the higher bandgap and better carrier mobility of these two ETL and HTL materials. The thickness optimization indicated that a thickness below 1000 nm is suitable for better performance which also leads to a good indication of making a lightweight solar cell. This study indicates that the use of low-cost and environment-friendly ZnO and NiO_x with non-toxic MAGeI_3 perovskite has the potential to obtain a high-efficiency eco-friendly solar cell
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