282 research outputs found
Enhancing delay fault coverage through low power segmented scan
No full textReducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low power DFT techniques and test generation procedures have been proposed. Segmented scan [17-20] has been shown to be an effective technique in addressing test power issues in industrial designs [18]. To achieve higher shipped product quality, tests for delay faults are becoming essential components of manufacturing test. This paper demonstrates, for the first time, that segmented scan facilitates increased delay fault coverage without degrading the reduction of the switching activity obtained by segmented scan. The increased transition delay fault coverage is achieved through careful selection of the capture cycle application. Experimental results on larger ISCAS-89 benchmarks show that using three segments, on average, fault coverage using launch off capture can be increased by about 5.4% while simultaneously reducing the peak switching activity caused by capture cycles by over 30%
On Test Program Compaction
No full textWhile compaction of binary test sequences for generic sequential circuits has been widely explore, the compaction of test programs for processor based systems is still an open area of research. Test program compaction is practically important because there are several scenarios in which Software-based Self-Test (SBST) is adopted, and the size of the test program is often a critical parameter. This paper is among the first to propose algorithms able to automatically compact an existing test program. The proposed solution is based on instruction removal and restoration, which is shown to significantly reduce the computational cost compared with instruction removal alone. Experimental results are reported, showing the compaction capabilities and computational costs of the proposed algorithms
New Techniques to Reduce the Execution Time of Functional Test Programs
No full textThe compaction of test programs for processor-based systems is of utmost practical importance: Software-Based Self-Test (SBST) is nowadays increasingly adopted, especially for in-field test of safety-critical applications, and both the size and the execution time of the test are critical parameters. However, while compacting the size of binary test sequences has been thoroughly studied over the years, the reduction of the execution time of test programs is still a rather unexplored area of research. This paper describes a family of algorithms able to automatically enhance an existing test program, reducing the time required to run it and, as a side effect, its size. The proposed solutions are based on instruction removal and restoration, which is shown to be computationally more efficient than instruction removal alone. Experimental results demonstrate the compaction capabilities, and allow analyzing computational costs and effectiveness of the different algorithms
Battery-aware dynamic voltage scaling in multiprocessor embedded system
No full textAbstract — In a battery powered system, a primary design consideration is the battery lifetime. Profile of current drawn from a battery determines its lifetime. Recently in [4] dynamic voltage scaling has been applied to alter the battery load current profile in distributed systems to reduce battery charge consumption. Load current profile is changed by utilizing the slack in the execution of the scheduled tasks. In this paper we propose a new dynamic voltage scaling procedure that alters load current profile by considering the total battery current instead of the method of [4] that considers the current dawn by individual task with the latest finish times in the schedule. The task schedule is partitioned into steps defined in this work and the load currents during selected steps are targeted for reduction by scaling the supply voltage of the processing elements. Experimental results on a large set of task graphs show that battery charge consumption reductions of up to 89.80 % are achieved by the new algorithm. I
A lightweight N-cover algorithm for diagnostic fail data minimization
No full textThe increasing design complexity of modern ICs has made it extremely difficult and expensive to test them comprehensively. As the transistor count and density of circuits increase, a large volume of fail data is collected by the tester for a single failing IC. The diagnosis procedure analyzes this fail data to give valuable information about the possible defects that may have caused the circuit to fail. However, without any feedback from the diagnosis procedure, the tester may often collect fail data which is potentially not useful for identifying the defects in the failing circuit. This not only consumes tester memory but also increases tester data logging time and diagnosis run time. In this work, we present an algorithm to minimize the amount of fail data used for high quality diagnosis of the failing ICs. The developed algorithm analyzes outputs at which the tests failed and determines which failing tests can be eliminated from the fail data without compromising diagnosis accuracy. The proposed algorithm is used as a preprocessing step between the tester data logs and the diagnosis procedure. The performance of the algorithm was evaluated using fail data from industry manufactured ICs. Experiments demonstrate that on average, 43% of fail data was eliminated by our algorithm while maintaining an average diagnosis accuracy of 93%. With this reduction in fail data, the diagnosis speed was also increased by 46%
Fault equivalence and dominance-based fault diagnosis
No full textFault diagnosis is performed to locate and identify physical failures in a defective integrated circuit. In this thesis, solutions to several problems in fault diagnosis are presented. First, techniques for identifying indistinguishable or functionally equivalent faults in combinational circuits are described. The techniques are based on implication of faulty values; and evaluation of faulty functions in cones of dominator gates of fault pairs. This is enhanced by utilizing circuit redundancy information. Static and dynamic methods are developed to exploit relations among inputs of dominator cones and further speed up the identification of equivalent fault pairs. Improvements compared to previous approaches are achieved in both the number of equivalent fault pairs identified and the time to prove equivalence. Second, theorems are introduced to identify indistinguishable fault pairs in synchronous sequential circuits using an iterative logic array of limited length. A theoretical framework for identification of sequential indistinguishability is developed utilizing information about reachable states, valid states and strongly connected components. Finally, an integrated approach for diagnosis is developed to accurately locate manufacturing defects. A fault model is used to encompass the behavior of a large variety of fault models and dominance relations among faults are used to reduce the list of candidate defect sites. Diagnosis techniques based on this fault model are described that accurately locate bridging defects and transition defects
Testing and diagnosis for systematic defects based on design-for-manufacturability guidelines
No full textThe occurrence of systematic defects is increasing with shrinking feature sizes of manufacturing processes. Design-for-manufacturability (DFM) rules and guidelines are layout constraints that are followed for ensuring yield and manufacturability. In spite of the use of DFM rules and guidelines, systematic defects may occur because complete information about process and fabrication defects is not available due to the decreasing window of time to market and the constraints on layout geometry. Noting that DFM guidelines already predict the most important sources of systematic defects, DFM guidelines are used in this dissertation as a basis for modeling, test generation and diagnosis for systematic defects. The basic process we use for this purpose is the following. Layout locations that are potential sites for systematic defects are found by tightening DFM guidelines. Affected transistors are identified at the schematic level, and defect behaviors are translated to gate level logic faults. Fault grading is applied to identify potential test holes. Additional test content is generated for improving test quality. Experimental results of this process were obtained for an Intel Pentium R 4 design demonstrating the feasibility of linking systematic defects and DFM guidelines. The methodology is extended to prioritize layout locations according to the importance of applying DFM guidelines to them. A higher priority is given to layout locations where failure to follow a DFM guideline will result in test holes due to defects that are hard-to-detect. The prioritized list can be used by layout tools to create circuits that are easier to test for systematic defects. We also investigate the use of DFM guidelines during the defect diagnosis process with the goal of identifying which DFM guidelines are responsible for the defects present in failing chips. We introduce a new metric called diagnostic coefficient that allows us to rank the guidelines according to their contribution of hard-to-diagnose defects. DFM guidelines that are ranked high should be applied earlier in order to obtain circuits that are easier to diagnose for systematic defects
High quality tests for transition faults
No full textGiven the rapid increase in the clock frequency of integrated circuits, the quality requirements of high-speed design necessitate delay fault testing. Transition faults are often used as a delay fault model due to the feasibility of test pattern generation and fault simulation for this model. In this thesis, we propose methodologies of generation and selection of high quality tests for transition faults. We first describe a new procedure of generating high quality weighted random patterns based on Markov sources for scan BIST targeting transition faults. We initially use statistics of deterministic tests for stuck-at faults in the design of a Markov source for transition faults. Then, by using statistics of tests for transition faults, we detect all the remaining detectable transition faults. Next, we propose and evaluate two metrics for selection of high quality delay tests out of a large given set of tests. In the path-based approach, we check the input transition patterns of each gate on an excited path and assign larger metric values to gates with a possibility of increased delays due to off-path inputs. In the cone-based approach, we trace the transitions from the inputs to the outputs of each cone in a circuit and perform a simple dynamic timing analysis to estimate a worst case delay. We then present a test generation procedure for transition faults that minimizes the detection of redundant transition faults in order to reduce unnecessary yield loss. We also propose rules for identifying dominance relations between redundant transition faults and detectable transition faults. We next propose a procedure of generating functional broadside tests for transition faults to further reduce unnecessary yield loss due to non-functional operation conditions of transition fault testing. The new test generation procedure consists of two phases and each phase uses a distinct strategy to generate functional broadside tests. The first phase uses simulation-based techniques and constrained test generation techniques. In the second phase, we apply a complete method using a sequential test generator for faults aborted in the first phase
Vision-Language Model for Robot Grasping
No full textRobot grasping is emerging as an active area of research in robotics as the interest in humanrobot interaction is gaining worldwide because of diverse industrial settings for sharing tasks and workplaces. It mainly focuses on the quality of generated grasps for object manipulation. However, despite advancements, these methods need to consider the human-robot collaboration settings where robots and humans will have to grasp the same objects concurrently. Therefore, generating robot grasps compatible with human preferences of simultaneously holding an object is necessary to ensure a safe and natural collaboration experience. In this work, we propose a novel, deep neural network-based method called CoGrasp that generates human-aware robot grasps by contextualizing human preference models of object grasping into the robot grasp selection process. We validate our approach against existing state-of-the-art robot grasping methods through simulated and real-robot experiments and user studies. In real robot experiments, our method achieves about 88% success rate in producing stable grasps that allow humans to interact and grasp objects simultaneously in a socially compliant manner. Furthermore, our user study with 10 independent participants indicated our approach enables a safe, natural, and socially aware humanrobot objects\u27 co-grasping experience compared to a standard robot grasping technique.To facilitate the grasping process, we also introduce a vision-language model that works as a pre-processing system before the grasping action takes place. In most settings, the robots are equipped with sensors that allow them to capture the scene, on which the vision model is used to do a detection task and objectify the visible contents in the environment. The language model is used to program the robot to make it possible for them to understand and execute the required sequence of tasks. Using the process of object detection, we build a set of object queries from the sensor image and allow the user to provide an input query for a task to be performed. We then perform a similarity score among these queries to localize the object that needs attention, and once identified, we can use a grasping process for the task at hand
Test generation considering operating conditions and diagnosis issues for large volume yield improvement
No full textTesting and fault diagnosis are performed to detect and identify failures in manufactured integrated circuits. In this thesis, solutions to two important problems in testing and diagnosis are proposed. First, we address the problem of test generation considering operating condition variations. Variations in operating conditions cause path delays to change, resulting in different sets of critical paths at different operating conditions. We propose a method of identifying critical paths over a specified range of operating conditions. We also propose a method of N-detection test generation for transition faults, where each fault is tested through one or more longest paths considering a range of operating conditions. Second we address the problems of improving the speed of diagnosis and identifying systematic defects from a large amount of diagnosis data. Both these aspects of diagnosis can potentially enable rapid high volume diagnosis and help increase the rate of improving yield, or even the final yield itself. To speed up diagnostic fault simulation we propose using a combination of structural preprocessing and concurrent equivalence identification techniques. The structural method aids equivalence identification and together the two techniques speed up diagnosis. We propose an analysis method to identify systematic defects from large volume diagnosis data using design or process parameters. We also show a method to improve analysis sensitivity using multiple parameters. Finally, we suggest a procedure to order the multiple analysis steps to find strongly associated parameters
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