1,720,995 research outputs found
Design and Optimization of Adaptable BCH Codecs for NAND Flash Memories
Full text linkNAND flash memories represent a key storage technology for solid-state storage systems. However, they suffer from serious reliability and endurance issues that must be mitigated by the use of proper error correction codes. This paper proposes the design and implementation of an optimized Bose-Chaudhuri-Hocquenghem hardware codec core able to adapt its correction capability in a range of predefined values. Code adaptability makes it possible to efficiently trade-off, in-field reliability and code complexity. This feature is very important considering that the reliability of a NAND flash memory continuously decreases over time, meaning that the required correction capability is not fixed during the life of the device. Experimental results show that the proposed architecture enables to save resources when the device is in the early stages of its lifecycle, while introducing a limited overhead in terms of are
ADAGE: An Automated Synthesis tool for Adaptive BCH-based ECC IP-Cores
Full text linkBose-Chaudhuri-Hocquenghem (BCH) codes are a family of Error Correction Codes (ECCs) largely applied in modern Flash-based Hard Disks to significantly improve their endurance and reliability. ADAGE is an advanced ESL tool for the automatic generation of BCH-based ECC IP-Cores with adaptable correction capability. End-users can freely and dynamically change it on-the-fly. In addition, ADAGE supports architectural exploration of both decoders and encoder
High Speed and Flexible Network Processing
Full text linkPacket filter technologies are facing new issues every day, as we had to re-engineer our computer networks in order to accommodate many new use cases. For instance, low-level network protocols are growing in number: new solutions, arising in particular for the purpose of network virtualization (e.g., 802QinQ, VXLAN), are rapidly transforming the Ethernet frames. The middle layers of the protocol stack are facing a similar metamorphosis: examples include the widespread adoption of Virtual Private Networks, or the necessity to transport IPv6 traffic over IPv4 networks. Packet filters are dramatically affected by those changes, as they become more complicated: it is important to be able to capture all the traffic we are interested in (e.g., web traffic), independently from the actual encapsulation used at lower layers. For this reason, the scientific research should embrace these new issues by proposing improvements over the traditional technologies, with the goal of maintaining the standards of efficiency of flexibility that we are used to. This dissertation addresses two specific issues: 1. How to preserve packet filter flexibility when specifying packet matching rules. We need a solution that allows a finer specification of matching rules, but that is also independent (if desired) on the specific encapsulation used at lower levels; moreover, the solution should support protocol definitions specified at run-time. Part I addresses the problem and describes in detail the proposed solution: NetPFL, a declarative language targeted to data-plane packet processing. 2. How to achieve efficiency when representing and combining multiple packet filters, even in case of bizarre and unusual network encapsulations. Part II outlines the issue and proposes two solutions: pFSA (described in Chapter 2) and its extension, xpFSA (delineated in Chapter 3
Model driven design of secure properties for vision-based applications: A case study
No full textIn this paper we discuss an approach to overcome difficulties and gaps which are typically encountered when dealing with security-oriented model-driven approaches. In particular, we state that state-of-the-art MDS approaches are not suitable for modern companies and industry in general, and address security only at a late stage of development, often causing big delays and reengineering costs due to extensive reworks. Instead, we propose to adopt in the SEcube platform an OTA-based XMDD approach to integrate security ab-initio. In addition, since our approach is based on a set of reusable SIBs organized within dedicated palettes in DIME, we decouple the issue of guaranteeing that the SIBs are correct and secure from the issue of analyzing the applications, which can be greatly simplified by knowing the characterization of each SIB in advance. We apply our approach to the concrete realm of computer vision steering robotics, present the safety and security properties elicited on the specific case study, and discuss the ways they can be enforce
On the impact of process variability and aging on the reliability of emerging memories (Embedded tutorial)2014 19th IEEE European Test Symposium (ETS)
No full textEf3S: An evaluation framework for flash-based systems
Full text linkNAND Flash memories are gaining popularity in the development of electronic embedded systems for both consumer and mission-critical applications. NAND Flashes crucially influence computing systems development and performances. EF3S, a framework to easily assess NAND Flash based memory systems performances (reliability, throughput, power), is presented. The framework is based on a simulation engine and a running environment which enable developers to assess any application impact. Experimental results show functionality of the framework, analysing several performance-reliability tradeoffs of an illustrative syste
On the impact of supply voltage variation on the statistical reliability of a Spin-transfer-torque MRAM (STT-MRAM)
No full textThe Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) presents as a promising alternative to today embedded memories due to its reduced read/write latency and high integration capability. Today aggressive technology scaling requirements, affects also the STT-MRAM by means of fabrication induced process variability and aging phenomena. These issues make reliability prediction a major concern. In this paper, we provide a methodology for predicting the reliability of an STT-MRAM based memory. The reliability prediction is performed at cell level, accounting for fabrication induced variability and aging phenomena simultaneously affecting the nMOS and MTJ devices. In addition, the effect of supply voltage variation on the cell reliability is also studied. The results show that a negative variation of the supply voltage highly degrades the cell reliability
An efficient many-core architecture for Elliptic Curve Cryptography security assessment
Full text linkAbstract. Elliptic Curve Cryptography (ECC) is a popular tool to con-struct public-key crypto-systems. The security of ECC is based on the hardness of the elliptic curve discrete logarithm problem (ECDLP). Im-plementing and analyzing the performance of the best known methods to solve the ECDLP is useful to assess the security of ECC and choose security parameters in practice. We present a novel many-core hardware architecture implementing the parallel version of Pollard’s rho algorithm to solve the ECDLP. This architecture results in a speed-up of almost 300 % compared to the state of the art and we use it to estimate the mon-etary cost of solving the Certicom ECCp-131 challenge using FPGAs.
ORIENTOMA: A novel platform for autonomous and safe navigation for blind and visually impaired
No full textThis work addresses the challenge behind the Orientoma project. Final aim of this project is to design and develop an effective, reliable and low-cost navigation system for blind and visually impaired people. The basic principle is to create a wearable system that acquires information from the context in which the user is, leveraging on modern smartphones and others smart devices and transmitting such information in a way that is understandable for the blind. Achieving this goal would be a significant improvement in the state of the art and would allow a better integration of the blind in active society. In this work we present the first outcomes of the project as well as the first prototype that has been implemented
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