1,721,105 research outputs found
Resistive switching memories based on metal oxides: Mechanisms, reliability and scaling
Full text linkWith the explosive growth of digital data in the era of the Internet of Things (IoT), fast and scalable memory technologies are being researched for data storage and data-driven computation. Among the emerging memories, resistive switching memory (RRAM) raises strong interest due to its high speed, high density as a result of its simple two-terminal structure, and low cost of fabrication. The scaling projection of RRAM, however, requires a detailed understanding of switching mechanisms and there are potential reliability concerns regarding small device sizes. This work provides an overview of the current understanding of bipolar-switching RRAM operation, reliability and scaling. After reviewing the phenomenological and microscopic descriptions of the switching processes, the stability of the low- and high-resistance states will be discussed in terms of conductance fluctuations and evolution in 1D filaments containing only a few atoms. The scaling potential of RRAM will finally be addressed by reviewing the recent breakthroughs in multilevel operation and 3D architecture, making RRAM a strong competitor among future high-density memory solutions
A Strong Physical Unclonable Function With Virgin State Embedded Phase Change Memory
Full text linkPhysical unclonable functions (PUFs) have gained attention in recent years due to the increasing demand for secure, compact, and power-efficient electronic devices in the Internet of Things (IoT). PUFs can provide a unique physical fingerprint to each device, which is a valuable means of enhancing security through the generation of unique and volatile cryptographic keys with no need to store them in nonvolatile memory (NVM). A major concern regarding PUF solutions for low-cost authentication is achieving robustness, a large challenge-response pair (CRP) space, and high reliability against environmental variations at the same time. In this work, we present a PUF system based on embedded phase change memory (PCM) in the virgin state with an industry-standard one-transistor/one-resistor (1T1R) cell, exploiting the wide resistance distribution as an entropy source. The PUF system is validated based on extensive physics-based simulations of embedded PCM cells integrated with 90-nm technology, showing raw reliability in temperature comparable with state-of-the-art solutions which can be further improved using dedicated schemes for the selection of reliable CRPs
Stochastic Memory Devices for Security and Computing
Full text linkWith the widespread use of mobile computing and internet of things, secured communication and chip authentication have become extremely important. Hardware-based security concepts generally provide the best performance in terms of a good standard of security, low power consumption, and large-area density. In these concepts, the stochastic properties of nanoscale devices, such as the physical and geometrical variations of the process, are harnessed for true random number generators (TRNGs) and physical unclonable functions (PUFs). Emerging memory devices, such as resistive-switching memory (RRAM), phase-change memory (PCM), and spin-transfer torque magnetic memory (STT-MRAM), rely on a unique combination of physical mechanisms for transport and switching, thus appear to be an ideal source of entropy for TRNGs and PUFs. An overview of stochastic phenomena in memory devices and their use for developing security and computing primitives is provided. First, a broad classification of methods to generate true random numbers via the stochastic properties of nanoscale devices is presented. Then, practical implementations of stochastic TRNGs, such as hardware security and stochastic computing, are shown. Finally, future challenges to stochastic memory development are discussed
Conductance variations and their impact on the precision of in-memory computing with resistive switching memory (RRAM)
No full textThis work addresses the reliability of RRAM, with a focus on conductance variation and its impact on in-memory computing (IMC). The core advantage of IMC is the ability to execute matrix-vector multiplication (MVM) in one step in crosspoint memory arrays, which can significantly accelerate data-intensive computing tasks, such as the inference and training of deep neural networks (DNNs). Since MVM is executed in the analogue domain, the imprecision of weight parameters stored in the memory array can result in errors which can affect the accuracy of the computation. By referring to a typical IMC device, that is the resistive switching memory (RRAM), we describe the conductance variations and stability with time, highlighting their impact on IMC accuracy. Then we discuss various options for mapping coefficients in the memory device, including multilevel, binary, unary, redundancy and slicing schemes, and their robustness with respect to conductance errors. It turns out that a tradeoff exists between accuracy and memory area occupation in the IMC circuit. Accurate IMC circuits thus must rely on the co-design of highly-precise, highly-stable devices and error tolerant mapping/computing schemes
A Generalized Block-Matrix Circuit for Closed-Loop Analog In-Memory Computing
Full text linkMatrix-based computing is ubiquitous in an increasing number of present-day machine learning applications such as neural networks, regression, and 5G communications. Conventional systems based on von-Neumann architecture are limited by the energy and latency bottleneck induced by the physical separation of the processing and memory units. In-memory computing (IMC) is a novel paradigm where computation is performed directly within the memory, thus eliminating the need for constant data transfer. IMC has shown exceptional throughput and energy efficiency when coupled with crosspoint arrays of resistive memory devices in open-loop matrix-vector-multiplication and closed-loop inverse-matrix-vector multiplication (IMVM) accelerators. However, each application results in a different circuit topology, thus complicating the development of reconfigurable, general-purpose IMC systems. In this article, we present a generalized closed-loop IMVM circuit capable of performing any linear matrix operation by proper memory remapping. We derive closed-form equations for the ideal input-output transfer functions, static error, and dynamic behavior, introducing a novel continuous-time analytical model allowing for orders-of-magnitude simulation speedup with respect to SPICE-based solvers. The proposed circuit represents an ideal candidate for general-purpose accelerators of machine learning
Invited Tutorial: Analog Matrix Computing with Crosspoint Resistive Memory Arrays
No full textMatrix computation is ubiquitous in modern scientific and engineering fields. Due to the high computational complexity in conventional digital computers, matrix computation represents a heavy workload in many data-intensive applications, e.g., machine learning, scientific computing, and wireless communications. For fast, efficient matrix computations, analog computing with resistive memory arrays has been proven to be a promising solution. In this Tutorial, we present analog matrix computing (AMC) circuits based on crosspoint resistive memory arrays. AMC circuits are able to carry out basic matrix computations, including matrix multiplication, matrix inversion, pseudoinverse and eigenvector computation, all with one single operation. We describe the main design principles of the AMC circuits, such as local/global or negative/positive feedback configurations, with/without external inputs. Mapping strategies for matrices containing negative values will be presented. The underlying requirements for circuit stability will be described via the transfer function analysis, which also defines time complexity of the circuits towards steady-state results. Lastly, typical applications, challenges, and future trends of AMC circuits will be discussed
Empirical metal-oxide RRAM device endurance and retention model for deep learning simulations
Full text linkMemristive devices including resistive random access memory (RRAM) cells are promising nanoscale low-power components projected to facilitate significant improvement in power and speed of Deep Learning (DL) accelerators, if structured in crossbar architectures. However, these devices possess non-ideal endurance and retention properties, which should be modeled efficiently. In this paper, we propose a novel generalized empirical metal-oxide RRAM endurance and retention model for use in large-scale DL simulations. To the best of our knowledge, the proposed model is the first to unify retention-endurance modeling while taking into account time, energy, SET-RESET cycles, device size, and temperature. We compare the model to state-of-the-art and demonstrate its versatility by applying it to experimental data from fabricated devices. Furthermore, we use the model for CIFAR-10 dataset classification using a large-scale deep memristive neural network (DMNN) implementing the MobileNetV2 architecture. Our results show that, even when ignoring other device non-idealities, retention and endurance losses significantly affect the performance of DL networks. Our proposed model and its DL simulations are made publicly available
Mitigating read-program variation and IR drop by circuit architecture in RRAM-based neural network accelerators
No full textIn-memory computing (IMC) with memory arrays allows reducing the time and energy consumption for matrix vector multiplication (MVM) for artificial neural networks (ANN) inference. However, the IMC accuracy is affected by nonidealities, such as program/read variations of device conductance and the parasitic voltage (IR) drop along the wires, whose impact quickly increases when increasing the array size. This work presents new IMC circuit architectures for mitigating both variations and IR drop at the same time. The new schemes allow for improving the accuracy of an ANN from 72.7% to 94.9%, compared to a software accuracy of 96.9%, at the expense of an increase of the memory array area
Bio-Inspired Techniques in a Fully Digital Approach for Lifelong Learning
Full text linkLifelong learning has deeply underpinned the resilience of biological organisms respect to a constantly changing environment. This flexibility has allowed the evolution of parallel-distributed systems able to merge past information with new stimulus for accurate and efficient brain-computation. Nowadays, there is a strong attempt to reproduce such intelligent systems in standard artificial neural networks (ANNs). However, despite some great results in specific tasks, ANNs still appear too rigid and static in real life respect to the biological systems. Thus, it is necessary to define a new neural paradigm capable of merging the lifelong resilience of biological organisms with the great accuracy of ANNs. Here, we present a digital implementation of a novel mixed supervised-unsupervised neural network capable of performing lifelong learning. The network uses a set of convolutional filters to extract features from the input images of the MNIST and the Fashion-MNIST training datasets. This information defines an original combination of responses of both trained classes and non-trained classes by transfer learning. The responses are then used in the subsequent unsupervised learning based on spike-timing dependent plasticity (STDP). This procedure allows the clustering of non-trained information thanks to bio-inspired algorithms such as neuronal redundancy and spike-frequency adaptation. We demonstrate the implementation of the neural network in a fully digital environment, such as the Xilinx Zynq-7000 System on Chip (SoC). We illustrate a user-friendly interface to test the network by choosing the number and the type of the non-trained classes, or drawing a custom pattern on a tablet. Finally, we propose a comparison of this work with networks based on memristive synaptic devices capable of continual learning, highlighting the main differences and capabilities respect to a fully digital approach
HfO2-based resistive switching memory devices for neuromorphic computing
Full text linkHfO2-based resistive switching memory (RRAM) combines several outstanding properties, such as high scalability, fast switching speed, low power, compatibility with complementary metal-oxide-semiconductor technology, with possible high-density or three-dimensional integration. Therefore, today, HfO2 RRAMs have attracted a strong interest for applications in neuromorphic engineering, in particular for the development of artificial synapses in neural networks. This review provides an overview of the structure, the properties and the applications of HfO2-based RRAM in neuromorphic computing. Both widely investigated applications of nonvolatile devices and pioneering works about volatile devices are reviewed. The RRAM device is first introduced, describing the switching mechanisms associated to filamentary path of HfO2 defects such as oxygen vacancies. The RRAM programming algorithms are described for high-precision multilevel operation, analog weight update in synaptic applications and for exploiting the resistance dynamics of volatile devices. Finally, the neuromorphic applications are presented, illustrating both artificial neural networks with supervised training and with multilevel, binary or stochastic weights. Spiking neural networks are then presented for applications ranging from unsupervised training to spatio-temporal recognition. From this overview, HfO2-based RRAM appears as a mature technology for a broad range of neuromorphic computing systems
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