1,721,005 research outputs found
Dual metal gate process scheme for wide range work function modulation and reduced Fermi level pinning
No full textEndurance reliability of multilevel-cell flash memory using a ZrO2/Si3N4 dual charge storage layer
No full textThe mechanisms of programming/erasing (P/E) and endurance degradation have been investigated for multilevel-cell (MLC) Flash memories using a Si(3)N(4) (NROM) or a ZrO(2)/Si(3)N(4) dual charge storage layer (DCSL). Threshold-voltage (V(th))-level disturbance is found to be the major endurance degradation factor of NROM-type MLCs, whereas separated charge storage and step-up potential wells give rise to a superior V(th)-level controllability for DCSL MLCs. The programmed V(th), levels of DCSL MLCs are controlled by the spatial charge distribution, as well as the charge storage capacity of each storage layer, rather than the charge injection. As a result, DCSL MLCs show negligible V(th)-level offsets (< 0.2 V) that are maintained throughout the 105 P/E cycles, demonstrating significantly improved endurance reliability compared to NROM-type MLCs
Dual Metal Gate Process by Metal Substitution of Dopant-Free Polysilicon on High-K Dielectric
No full textNovel ZrO2/Si3N4 Dual Charge Storage Layer to Form Step-Up Potential Wells for Highly Reliable Multi-Level Cell Application
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