1,721,091 research outputs found
Ultra-Thin Body Silicon- on-Insulator (UTB SOI) MOSFET with Metal Gate Work-Function Engineering for Sub-70nm Technology Node
No full textReduction of Direct- Tunneling Gate Leakage Current in Double-Gate and Ultra-Thin Body MOSFETs
No full textThis research is supported under MARCO contract 2001-MT-88
Ultra-thin Body SOI MOSFET for Deep-Sub-Tenth Micron Era
No full text\DARPA AME Program under Contract N66001-
97-1-89 1
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Compact Models for Future Generation CMOS
Full text linkMultiple-gate MOSFETs with superior short channel control are expected to replace planar CMOS in the near future. An accurate and computationally efficient compact transistor model is necessary to simulate circuits in multiple-gate MOSFET technologies. In this dissertation research, a compact multiple-gate MOSFET model, BSIM-MG is developed. BSIM-MG includes independent multi-gate compact model BSIM-IMG and common multi-gate compact model BSIM-CMG. We focus on BSIM-IMG for multiple-gate MOSFETs with independent front- and back-gates. The basic formulations for surface potential, drain current and charge are derived and verified against TCAD simulations with excellent agreements. The model preserves important property of multi-gate MOSFETs such as volume inversion. Non-ideal effects including short channel effects, length dependent back-gate coupling, transport models, leakage currents, parasitic resistances and capacitances, temperature effects and self heating are considered in the model. The model expressions are carefully formulated so that the symmetry of the source and drain is preserved. Rules for maintaining symmetry are discussed in this dissertation.For the common multi-gate transistor model BSIM-CMG, the basic expressions have been improved so that it is compatible with a novel non quasi-static effects modeling technique — charge segmentation. In addition, a parasitic source/drain resistance model is developed, including three components: the contact resistance, the spreading resistance, and the bias-dependent extension resistance. Both BSIM-CMG and BSIM-IMG models are verified against TCAD and measured data.The use of the FinFET compact model to model manufacturing variation in a FinFET technology is further explored. The model matches measured data well for both the nominal case and the statistical distribution for NMOS threshold voltage as well as the read static noise margin. A non-Gaussian threshold voltage distribution is observed for nFET devices, and the compact model successfully captures the distribution. We further outlined and demonstrated a Monte-Carlo based procedure for designing FinFET SRAM cells using the extracted variation information.Technology scaling has enabled numerous CMOS analog circuits for low cost radio-frequency applications. The modeling of MOSFET thermal noise becomes very important. In the final part of this dissertation research, a new thermal noise model is developed for the industry standard BSIM4 model that enhances the existing thermal noise formulation in BSIM4. The model is verified against a segmented channel MOSFET model as well as measured data. It is implemented in Berkeley SPICE3 and is ready for industry use. A method to port the model to BSIM-MG for thermal noise modeling in multi-gate MOSFETs is also presented
Band-to-Band Tunnel Transistor Design and Modeling for Low Power Applications
Full text linkAs the physical dimensions of the MOSFET have been scaling, the supply voltage has not scaled accordingly and thus the power density has been continuously increasing. This is mainly due to the fact that transistor operation requires carriers to go over the source side potential barrier which limits the subthreshold swing of a MOSFET to 60mV/dec at room temperature and thus inhibits the scaling of the threshold voltage. Tunneling devices utilizing the band-to-band tunneling mechanism have been known to overcome this fundamental limit.In this thesis, the tunneling field-effect-transistor (TFET) is explored to replace conventional MOSFETs for low power applications. The band-to-band tunneling mechanism is looked into in order to develop a more accurate tunneling model that considers the change in effective mass during the transition between the conduction and valence band. Device simulator parameters are modified with this model and are used in designing the TFET. The silicon P-I-N structure TFET is studied through simulation and various experimental splits as a baseline for the TFET development. High tunneling currents are measured from a short channel device with a flash and spike anneal combination and a novel silicided source TFET using silicide induced dopant segregation is shown to achieve sub-60mV/dec subthreshold swing. Measurement and analysis methods of the transistor current and subthreshold swing to verify the TFET are discussed. Lower band gap Ge devices and Strained Si/Ge hetero-structure devices utilizing a lower effective bandgap are also explored to improve the performance of the TFET
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Compact Modeling of Advanced CMOS and Emerging Devices for Circuit Simulation
Full text linkCompact model plays an important role in designing integrated circuits and serves as a bridge to share the information between foundries and circuit designers. Since various flavors of transistor architectures like FDSOIs and FinFETs are proposed to improve device performances, the accurate, fast, and robust compact models, which are capable of reproducing the very complicated transistor characteristics like transconductance, are urgently required. Novel device concept, such as tunnel FETs (TFETs) and negative capacitance FETs (NCFETs), needs new device modeling methodology and understanding of device physics. In addition to transistors, memory device like magnetic tunnel junction (MTJ) compact model is also crucial for circuit designs. This dissertation presented the advanced research on compact models for the state-of-the art transistor and memory technologies: FDSOIs, FinFETs, TFETs, NCFETs, and MTJs.Due to the limitations in the aggressively scaled planar transistors, the devices with good electrostatic control are discussed and modeled into the industry standard model - BSIM-IMG for FDSOIs and BSIM-CMG for multi-gate FETs. Although the dynamic back-gate bias change help reduce the static power in FDSOIs, the leakages, overlap capacitance, and carrier transport are thus showing back-gate bias-dependence. The enhanced gate-related leakage, overlap capacitance, and mobility compact models are validated against the silicon data and incorporated into BSIM-IMG. The leakages through subsurface path and source-to-drain direct tunneling due to extremely short channel are also included in this work, which are in excellent agreement with the technology computer-aided design (TCAD) and atomistic simulations. The computationally efficiency of these models are the key solutions for evaluating the circuit performance of future technology nodes.Two paradigms of steep subthreshold slope transistors - TFETs and NCFETs as the promising candidates for future Internet of Things (IoT) and logic/analog applications are also presented in this thesis. TFET has a gated p-i-n diode structure, where the current relies on direct band-to-band tunneling in source/channel junction. Such tunneling mechanism breaks the tradition limitation of MOSFET turn-ON characteristics called the Boltzmann tyranny. The improvements in power consumption and delay of circuits are thus the emphasis and attention of device community, where the need of TFET compact model is fulfilled with the developed model in this work. NCFET is rapidly emerging as a preferred replacement for traditional MOSFET since the recent discovery of ferroelectric (FE) materials to amplify the voltage suggests that further scaling supply voltage is possible with the CMOS-compatible fabrication process of NCFET. The short channel effect, ferroelectric variability, and spacer optimization design are the focus in this thesis. The compact model of NCFET is improved to be more predictive for ferroelectric properties with verification against TCAD simulations. Monte-Carlo method is carried out in FE variability study, where the main finding is that the dielectric phase is critical but fortunately is theoretically possible to be absent. The spacer design reveals that further engineering the capacitance matching via parasitic capacitance is the key solution for future technology nodes.In addition to transistor compact models and physics, the memory device - spin-transfer-torque magnetic tunnel junction (STT-MTJ) is also presented. The resistances and critical currents are derived from the Landau-Lifshitz-Gilbert (LLG) equation and modeled analytically. The RC sub-circuit is found to describe the dynamic switching behavior of MTJ due to the precession and thermal fluctuation. The proposed MTJ compact model has been validated with silicon data from the industry and is capable of simulating a memory circuit with previously mentioned BSIM models
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Negative Capacitance Field-Effect Transistor Design and Machine Learning Applications in Compact Models
Full text linkWith the scaling of the transistor, fabrication of an actual device and modeling of an ultra-short channel transistor becomes more and more challenging. Dr. Salahuddin proposed a negative capacitance field-effect transistor (NCFET) in 2008. By utilizing the ferroelectric negative capacitance region with proper capacitance matching a ferroelectric layer with a dielectric layer, the overall effective oxide thickness could be further thinned down without affecting much of the carrier mobility.A technique of optimization of an NCFET will be proposed in chapter 2. By utilizing process techniques like mask oxidation, a non-uniform interfacial layer can be formed to create a more uniform metal-oxide-semiconductor capacitance along the channel (Cmos). The overall capacitance matching of an NCFET can be improved because of a uniform Cmos profile. Chapter 3 will introduce a simulation scheme of NCFETs variation due to dielectric grains within a ferroelectric film. This scheme can be applied to the future estimation of NCFETs variation given the grains' size and the ferroelectric parameters.
The effect and compact modeling of the polarization gradient effect will be demonstrated in Chapter 4. With the feature of polarization gradient effect in an NCFET compact model, the characteristics of an NCFET can be better captured, such as negative drain resistance and negative drain-induce barrier
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effect (DIBL). Energy analysis of an NCFET will be presented in Chapter 5. The consistency between TCAD energy calculation by the integral over the grids with the Landau equation and power consumption calculation from the circuit is shown in detail.
Negative capacitance benefits on FinFET and gate-all-around (GAA) FET will be presented in chapters 6 & 7, respectively. Baseline devices of a FinFET and a GAAFET are made in technology computer-aided design (TCAD) and are calibrated to International Roadmap for Devices and Systems (IRDS) tables. NC parameters are also extracted from an experiment on metal-oxide-semiconductor capacitance (MOSCAP). How many nodes NC extends the baseline will be discussed. A compact model of an anti-ferroelectric on an NCFET will be presented in Chapter 8.
Potential applications of machine learning will be illustrated in Chapters 9 & 10. Machine learning-assisted parameter extraction will be presented in Chapter 9. In the long run, using machine learning-assisted models as an alternative to the conventional equation-based compact models will be shown in Chapter 10. In the end, Chapter 11 will conclude chapters and propose some future work
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