29,789 research outputs found

    Nanoscale CMOS spacer FinFET for the terabit era

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    A spacer lithography process technology, which uses a sacrificial layer and spacer layer formed by chemical vapor deposition (CVD), has been developed. It has been applied to make a sub-40-nm Si-fin structure for a double-gate FinFET with conventional dry etching for the first time. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this spacer lithography technology yields better critical dimension uniformity than conventional optical or e-beam lithography and defines smaller features beyond the limit of current lithography technology. It also provides a doubling of feature density for a given lithography pitch, which increases current by a factor of two. To demonstrate this spacer lithography technology, Si-fin structures have been patterned for planar double-gate CMOS FinFET devices.The authors would like to thank the University of California- Berkeley Microlab staffs for their support in device fabrication

    A spacer patterning technology for nanoscale CMOS

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    A spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching. The minimum-sized features are defined not by the photolithography but by the CND film thickness. Therefore, this technology yields critical dimension (CD) variations of minimum-sized features much smaller than that achieved by optical or e-beam lithography. In addition, it also pro-tides a doubling of device density for a given lithography pitch. This method is used to pattern silicon fins for double-gate metal-oxide semiconductor field effect transistors (MOSFETs) (FinFETs) and gate electrode structures for ultrathin body MOSFETs. Process details are presented.This work was supported in part by the DARPA AME Program under Contract N66001-97-1-8910 and the SRC under Contract 2000-NJ-850

    New synonyms and combinations in Asiatic Ardisia (Myrsinaceae)

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    Studies on the genus Ardisia Sw. for Flora Malesiana have led to the reduction of 95 taxa to synonymy, seven species to the infraspecific level: A. demissa Miq. var. bambusetorum (King & Gamble) C.M. Hu, A. polysticta Miq. subsp. punctipelata (Merr.) C.M. Hu, A. ternatensis Scheff. var. forstenii (Scheff.) C.M. Hu, A. darlingii Merr. subsp. podadenia (Stone) C.M. Hu, A. imperialis K. Schum. var. novoguineensis (Mez) C.M. Hu, A. pubicalyx Miq. var. collinsae (Fletcher)C.M. Hu, A. tahanica King & Gamble subsp. eucalyptifolia (Stone) C.M. Hu, and two new combinations are made: A. forbesii S. Moore var. cataractorum (Stone) C.M. Hu, A. fulva King & Gamble var. multiflora (Stone) C.M. Hu

    Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain

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    Nanoscale ultrathin body (UTB) p-channel MOSFETs with body thickness down to 4 nm and raised source and drain (S/D) using selectively deposited Ge are demonstrated for the first time. Devices with gate length down to 30 mn show high drive current, low off current, and excellent short-channel behavior. Mobility enhancement and threshold-voltage shift due to the quantum confinement of inversion charge in the ultrathin body are investigated

    The politics and economics of regulatory impact assessment

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    This is the author accepted manuscript. The final version is available from the publisher via the link in this record
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