9,809 research outputs found
Deep Learning Processors for On-Device Intelligence
No full textRecently, deep learning is influencing not only the technology itself but also our everyday lives. Formerly, most AI functionalities and applications were centralized on datacenters. However, the primary platform for AI has recently shifted to on-devices. With the increasing demand on edge, mobile and IoT AI, conventional hardware solutions face their ordeal because of their low energy efficiency on such power hungry applications. For the past few years, dedicated DNN inference accelerators have been under the spotlight. However, with the rising emphasis on privacy, personalization and local optimization, ability to learn is becoming the second hurdle for “on-device AI.” In addition, with the recent developments in hardware research, faster DNN processing speed with low power consumption is achieved, enabling numerous applications on edge and mobile devices, which were formerly not applicable to edge and mobile devices. Applications with humanistic intelligence, which can take users' emotion into account, have been demonstrated, along with GAN and DRL as well as AI models using 3-dimensional data processing for higher accuracy
1.2 Intelligence on Silicon: From Deep-Neural-Network Accelerators to Brain Mimicking AI-SoCs
No full textWhile, currently, Artificial-Intelligence technology is affecting all industrial paradigms, it is also impacting lifestyle of all society. AI technology is widely used in most information hardware, software, and networking, underlying all consumer technology: smartphones, home appliances, and the Web
Mobile deep learning processors on the edge
No full textPresents a collection of slides containing the following topics: deep neural network; DNN hardware; cloud computing; edge computing; mobile DNN inference processors; DNN processor flexibility; mobile DNN learning processors; and reinforcement learning processors
Fabric Circuit Board-Based Dry Electrode and its Characteristics for Long-Term Physiological Signal Recording
No full textEmerging low energy Wearable Body Sensor Networks using patch sensors for continuous healthcare applications
No full textDirect Feedback Alignment Based Convolutional Neural Network Training for Low-Power Online Learning Processor
No full textThere were many algorithms to substitute the back-propagation (BP) in the deep neural network (DNN) training. However, they could not become popular because their training accuracy and the computational efficiency were worse than BP. One of them was direct feedback alignment (DFA), but it showed low training performance especially for the convolutional neural network (CNN). In this paper, we overcome the limitation of the DFA algorithm by combining with the conventional BP during the CNN training. To improve the training stability, we also suggest the feedback weight initialization method by analyzing the patterns of the fixed random matrices in the DFA. Finally, we propose the new training algorithm, binary direct feedback alignment (BDFA) to minimize the computational cost while maintaining the training accuracy compared with the DFA. In our experiments, we use the CIFAR-10 and CIFAR-100 dataset to simulate the CNN learning from the scratch and apply the BDFA to the online learning based object tracking application to examine the training in the small dataset environment. Our proposed algorithms show better performance than conventional BP in both two different training tasks especially when the dataset is small. Furthermore, we examined the efficiency improvement by real chip implementation, and finally, DNN training accelerator with BDFA shows 35.3% lower power consumption compared with hardware which is optimized for BP
A study of pipeline architectures for high-speed synchronous DRAMs
No full textThe performances of SDRAM's with different pipeline architectures are examined analytically on the basis of the time required to refill the on-chip cache of a Pentium CPU. The analysis shows that the cycle time of the conventional pipeline structures cannot be reduced because of its difficulty in distributing the access time evenly to each pipeline stage of the column address access path. On the contrary, the wave pipeline architecture can make the access path evenly divided and can increase the number of pipeline stages to achieve the shortest cache refill time. But the wave congestion at the output terminal of the wave pipeline path caused by access time fluctuation narrows the valid time window. The parallel registered wave pipeline architecture can remove the effect of access time fluctuation so that the cycle time is defined only by the data pulse width. If the data pulse width t(w) < 2 ns, even 500-MHz clock frequency can be obtained.
Your heart on your sleeve: Advances in textile-based electronics are weaving computers right into the clothes we wear
No full textWearable health care is part of the more general category of wearable computers or wearable electronics. Wearable electronics and wearable computers appeared in the mid-1990s, when the computer was regarded as the ultimate equipment for information processing and before laptop computers, tablet computers, and smartphones. At that time, people tried to find what kind of portable form factors would be good for the computer as an information device for daily living. Wearable computers refers to miniature electronic devices that are worn under, with, or on top of clothing [1]. With the help of humancomputer interaction (HCI) technology, which previously made use of the ?windows? concept, as Web browsers do, by means of a graphic user interface (GUI), wearable electronics have tried to use other modalities for HCI beyond the display and keyboard. In many respects, the current smartphone has already achieved the computing power the early wearable computers aimed at. But in addition to the smartphone?s strong computing power, more human body?compatible, wearable IO devices and sensors are necessary so that users can experience the full benefits of mobile computing, which the smartphone and tablet PC have begun to open up. In many applications, the user?s skin, hands, voice, eyes, and arms, as well as the user?s motion or attention, are actively exploited in appropriate engagement with the physical environment. Of course, this area shares many basic technologies with the mobile computing, ambient intelligence, and ubiquitous-computing research communities, including those that handle power management and heat dissipation, software architectures, and wireless and personal-area networks. © 2009-2012 IEEE
C-DNN V2: Complementary Deep-Neural-Network Processor with Full-Adder/OR-based Reduction Tree and Reconfigurable Spatial Weight Reuse
No full textIn this article, we propose a Complementary Deep-Neural-Network (C-DNN) processor V2 by optimizing the performance improvement from combination of CNN and SNN. C-DNN V1 showcased the potential for achieving higher energy efficiency by combining CNN and SNN. However, it encountered 5 challenges that hindered the full realization of this potential: Inefficiency of the clock gating accumulator, imbalance in spike sparsity across different time-steps, redundant cache power stemming from temporal weight reuse, limited performance of the SNN core for dense spike trains, and nonoptimal operation resulting from tile-based workload division. To overcome these challenges and achieve enhanced energy efficiency through the CNN-SNN combination, C-DNN V2 is developed. It addresses these challenges by implementing a Full-Adder/OR-based reduction tree, which reduces power consumption in the SNN core under high spike sparsity conditions. Additionally, it efficiently manages spike sparsity imbalances between dense and sparse SNN cores by integrating them simultaneously. The proposed reconfigurable spatial weight reuse method decreases the number of redundant register files and their power consumption. The spike flipping and inhibition method facilitate efficient processing of input data with high spike sparsity in the SNN core. Furthermore, fine-grained workload division and a high sparsity-aware CNN core are introduced to ensure optimal processing of each data in the domain with the highest energy efficiency. In conclusion, we propose the C-DNN V2 as an optimal complementary DNN processor, delivering 76.9% accuracy for ImageNet classification with a state-of-the-art energy efficiency of 32.8 TOPS/W.
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