197,099 research outputs found
Diagnosis of Multiple-Voltage Design with Bridge Defect
No full textMultiple voltage is an effective dynamic power reduction design technique commonly used in low-power ICs. To the best of our knowledge, there is no reported work for diagnosing multiple-voltage enabled ICs, and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. By using synthesized ISCAS benchmarks, with realistic extracted bridges and a parametric fault model, this paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multivoltage diagnosis algorithm. In addition, it also identifies the most useful voltage settings to reduce diagnosis cost by eliminating tests at certain voltage setting using the proposed multivoltage diagnosis approach, thereby achieving high diagnosis accuracy at reduced cost
Scan architecture with mutually exclusive scan segment activation for shift and capture power reduction
No full textPower dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum transition don't care fill, special scan cells and scan chain partitioning), very little work has been carried out towards reducing the peak power during test response capture and the few existing approaches for reducing capture power rely on complex ATPG algorithms. This paper proposes a scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches. The proposed architecture achieves both shift and capture power reduction with no impact on the performance of the design, and with minimal impact on area and testing time (typically 2-3%). An algorithmic procedure for assigning flip-flips to scan segments enables reuse of test patterns generated by standard ATPG tools. An implementation of the proposed method had been integrated into an automated design flow using commercial synthesis and simulation tools which was used on a wide range of benchmark designs. Reductions up to 57% in average power, and up to 44% and 34% in peak power dissipation during shift and capture cycles, respectively, were obtained when using two scan segments. Increasing the number of scan segments to six leads to reductions of 96% and 80% in average power and respectively maximum number of simultaneous transitions
Numerically efficient modeling of CNT transistors with ballistic and non-ballistic effects for circuit simulation
No full textThis paper presents an efficient carbon nanotube (CNT) transistor modeling technique which is based on cubic spline approximation of the non-equilibrium mobile charge density. The approximation facilitates the solution of the selfconsistent voltage equation in a carbon nanotube so that calculation of the CNT drain-source current is accelerated by at least two orders of magnitude. A salient feature of the proposed technique is its ability to incorporate both ballistic and nonballistic transport effects without a significant computational cost. The proposed models have been extensively validated against reported CNT ballistic and non-ballistic transport theories and experimental results
Combined Time and Information Redundancy for SEU-Tolerance in Energy-Efficient Real-Time Systems
No full textRecently the trade-off between energy consumption and fault-tolerance in real-time systems has been highlighted. These works have focused on dynamic voltage scaling (DVS) to reduce dynamic energy dissipation and on time redundancy to achieve transient-fault tolerance. While the time redundancy technique exploits the available slack time to increase the fault-tolerance by performing recovery executions, DVS exploits slack time to save energy. Therefore we believe there is a resource conflict between the time-redundancy technique and DVS. The first aim of this paper is to propose the usage of information redundancy to solve this problem. We demonstrate through analytical and experimental studies that it is possible to achieve both higher transient fault-tolerance (tolerance to single event upsets (SEU)) and less energy using a combination of information and time redundancy when compared with using time redundancy alone. The second aim of this paper is to analyze the interplay of transient-fault tolerance (SEU-tolerance) and adaptive body biasing (ABB) used to reduce static leakage energy, which has not been addressed in previous studies. We show that the same technique (i.e. the combination of time and information redundancy) is applicable to ABB-enabled systems and provides more advantages than time redundancy alone
Workload-Ahead-Driven Online Energy Minimization Techniques for Battery-Powered Embedded Systems with Time-Constraints
No full textThis paper proposes a new online voltage scaling (VS) technique for battery-powered embedded systems with real-time constraints. The VS technique takes into account the tasks execution times and discharge currents to further reduce the battery charge consumption when compared to the recently reported slack forwarding technique, whilst maintaining low online complexity of O(1). Furthermore, we investigate the impact of online rescheduling and remapping on the battery charge consumption for tasks with data dependency which has not been explicitly addressed in the literature and propose a novel rescheduling/remapping technique. We demonstrate and compare the efficiency of the presented techniques using seven real-life benchmarks and numerous automatically generated examples
Battery-aware dynamic voltage scaling in multiprocessor embedded system
No full textAbstract — In a battery powered system, a primary design consideration is the battery lifetime. Profile of current drawn from a battery determines its lifetime. Recently in [4] dynamic voltage scaling has been applied to alter the battery load current profile in distributed systems to reduce battery charge consumption. Load current profile is changed by utilizing the slack in the execution of the scheduled tasks. In this paper we propose a new dynamic voltage scaling procedure that alters load current profile by considering the total battery current instead of the method of [4] that considers the current dawn by individual task with the latest finish times in the schedule. The task schedule is partitioned into steps defined in this work and the load currents during selected steps are targeted for reduction by scaling the supply voltage of the processing elements. Experimental results on a large set of task graphs show that battery charge consumption reductions of up to 89.80 % are achieved by the new algorithm. I
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
No full textSupply voltage scaling and adaptive body-biasing are important tech-niques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting the voltage and performance settings according to the application needs. In order to take full ad-vantage of slack that arises from variations in the execution time, it is important to recalculate the voltage (performance) settings during run-time, i.e., online. However, voltage scaling (VS) is computationally ex-pensive, and thus significantly hampers the possible energy savings. To overcome the online complexity, we propose a quasi-static voltage scal-ing scheme, with a constant online time complexity O(1). This allows to increase the exploitable slack as well as to avoid the energy dissipated due to online recalculation of the voltage settings. We conduct several experiments that demonstrate the advantages of the proposed technique over the previously published voltage scaling approaches
Application of Analog Adaptive Filters for Dynamic Sensor Compensation
No full textThis paper investigates the application of analog adaptive techniques to the area of dynamic sensor compensation, of which there is little reported work in the literature. The case is illustrated by showing how the response of a load cell can be improved to speed up the process of measurement. The load cell is a sensor with an oscillatory output in which the measurand contributes to the response parameters. Thus, a compensation filter needs to track variation in measurand whereas a simple, fixed filter is only valid at one specific load value. To facilitate this investigation, computer models for the load cell and the adaptive compensation filter have been developed. To allow a practical implementation of the adaptive techniques, a novel piecewise linearization technique is proposed in order to vary a floating voltage-controlled resistor in a linear manner over a wide range. Simulation and practical results are presented, thus demonstrating the effectiveness of the proposed techniques
Dynamic Sensor Compensation Using Analogue Adaptive Filter Compatible with Digital Technology
No full textAn analogue adaptive filter for dynamic response compensation of a load cell sensor is presented. The filter employs only transistors and therefore it can be integrated using standard digital CMOS technology, which is suitable for System-on-Chip applications. To perform adaptive compensation over a wide range of measurand, a novel CMOS multiplier circuit was developed. The analogue adaptive filter has been designed and simulated using 0.35µm 3.3V BSim3v3 CMOS foundry models and found to achieve effective compensation
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