1,721,027 research outputs found
Behavioral models of electronic filters
This paper describes how generic behavioural filter models are developed. The models are implemented using the analogue behavioural modelling (ABM) feature of PSpice. To demonstrate the use of the models, a number of simulation examples are included
New dual output transconductance amplifier based biquad
A new current mode biquad filter configuration based on dual output OTA is presented. Design equations of various filter functions and sensitivity expressions are given. Based on a discrete bipolar transistor realisation and the cascade approach, the measured frequency results of 4th-order lowpass 5.5MHz Butterworth filter is included
On the implementation of video filters using current feedback amplifiers
This paper describes the design and practical realisation of 5.5MHz lowpass elliptic lowpass filter with group delay equalisation using current feedback amplifiers. Measured results show that it is possible to obtain video specification filter using active implementation
Understand the Fundamental of Passive Video Filters
Designing a passive anti-aliasing video filter requires good understanding of the key elements in such a circuit. Such filters must generally have low passband ripple, a sharp transition band, high stop band attenuation, and linear phase or flat group delay response. This article describes in detail the design of video passive filters including elliptic filters, group-delay and amplitude equalisation. Measured results of typical video filters are included
On the practical implementation of high performance active audio filters using the FDNR concept
This paper describes the practical realisation of high performance active filters for digital audio applications. The filters are based on the Frequency Dependent Negative Resistor design method. Measured results of practical realisation based on thickfilm technology are presented
Reduction of latency and resource usage in bit-level pipelined data paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimised towards specific applications are used. This paper describes a novel methodology for the design of generic bit-level pipelined data paths that have the low resource usage and latency of specifically tailored architectures but still allow the flexible trade-off between speed and resource requirements inherent in generic circuits. This is achieved through the elimination of all skew and alignment flip-flops from the data path whilst still maintaining the original pipelining scheme, hence allowing more compact structures with decreased circuit delays. The resulting low latency is beneficial in the realisation of all recursive signal processing applications and the reduced resource usage enables particularly the efficient FPGA realisation of high performance signal processing functions. The design process is illustrated through the high level-based FPGA realisation of a 9th-order wave digital filter, demonstrating that high performance and efficient resource usage are possible. For example, the implementation of a digital filter with 10-bit signal word length and 6-bit coefficients using a Xilinx XC4013XL-1 device supports sample rates of 2.5MH
- …
