14 research outputs found
Synthesis of Clock Gating Logic through Factored Form Matching
No full textClock gating is typically dictated by designers in register transfer level (RTL). Automatic synthesis of clock gating in gate level has been less explored, but is certainly more convenient to designers; it can also complement RTL clock gating by extracting additional gating conditions. The key problem in gatelevel clock gating synthesis is to implement gating conditions with minimum amount of additional logic. In this paper, we aim to utilize the existing combinational logic as much as possible. This is done by extracting a factored form (modeled by a factoring tree) of each gating condition, and try to cover the tree by factoring trees of existing combinational logic; the corresponding process is named factored form matching. Experiments demonstrate that the proposed matching achieves 25% reduction in the number of gates to implement gating conditions; this can be compared to prior method using Boolean division, which achieves 10% reduction
Chemisorption of NH3 on Monomeric Vanadium Oxide Supported on Anatase TiO2: A Combined DRIFT and DFT Study
No full textV/TiO2 catalysts are used in various reactions, including oxidative dehydrogenation, partial oxidation of ethanol, and selective catalytic reduction of NOx with NH3. In this work, we investigated the effect of supported monomeric vanadium oxide (VO3) on the acidity of anatase TiO2(101) surface by using density functional theory calculations combined with in situ diffuse reflectance infrared Fourier transform (DRIFT) experiments. The hydrogenation of TiO2 to form hydroxyl groups on the surface was energetically more favorable in the presence of the supported monomeric vanadium oxide. Charge transfer between TiO2 support and VO3 was considered as an origin of −OH stabilization, which made Brønsted acid sites more abundant on the V/TiO2 surface than on TiO2. Moreover, it was observed that the cationic vanadium center in VO3 can act as much weaker Lewis acid sites than the titanium center in TiO2. Such weakened acidity of Lewis acid sites in the presence of monomeric vanadium oxide was consistently observed in in situ DRIFT results, which could explain the higher reactivity of NH3 adsorbed on Lewis acid sites of V/TiO2 than those of TiO2 in the NH3-selective catalytic reduction reaction.11sciescopu
Clock Gating Synthesis of Netlist with Cyclic Logic Paths
No full textGate-level clock gating is to synthesize clock gating structure (grouping of registers and extracting gating function of each group) from a netlist. We note that a simpler gating function can be derived from a cyclic logic path that connects the input and output of the same register. Another benefit comes from the fact that simplifying the cyclic paths using the derived gating function as don't-care is straightforward. A key problem in this approach is to extract a set of cyclic paths of each register, such that power consumption is minimized and circuit timing is left intact. Experiments demonstrate that power consumption is reduced by 49% on average of test circuits (with initial ungated netlist as a reference), while a sample previous gate-level clock gating achieves 34% of power saving
Buffer insertion to remove hold violations at multiple process corners
No full textBuffer insertion to remove hold violations at multiple process corners is addressed for the first time. The problem is formulated as integer linear programming (ILP); it is combined with circuit partitioning heuristic so that larger circuits can also be handled. A heuristic buffer insertion algorithm is then proposed and compared to ILP, which demonstrates only a slight increase of the number of buffers (2.4% on average). Two additional intuitive methods are implemented to demonstrate why new heuristic algorithm is needed: conventional buffer insertion at each process corner one by one and conventional buffer insertion at all process corners simultaneously followed by combining insertion results
