1,721,086 research outputs found
Partial coding algorithm for area and energy efficient crosstalk avoidance codes implementation
No full textModern interconnect performance is greatly affected by crosstalk noise because of continuous decrease in wire separation and increase in its aspect ratio with technology scaling. Such noise is highly dependent on data transition patterns, coding techniques have been proposed to alleviate crosstalk delay by controlling these patterns. The complexity of available crosstalk avoidance codes, along with their associated overheads, increase rapidly with bus width. The lack of energy and area-efficient method to implement such codes has so far prevented their use in practical designs. This study presents a generic framework, which allows efficient implementations of crosstalk avoidance codes; the essence of the proposed approach is based on the partial coding concept. Quantitative analysis performed in 32 nm technology shows that substantial savings in area and energy costs can be obtained using the proposed technique compared with both existing coding solutions and conventional methods as shielding and repeater insertion
Secure Hardware Design of IoT Nodes using Physically Unclonable Functions
No full textThe Internet of Things (IoT) consists of numerous inter-connected resource-constrained devices such as sensors nodes and actuators, which are linked to the Internet. By 2020 it is anticipated that the IoT paradigm will include approximately 20 billion connected devices. The interconnection of such devices provides the ability to collect a huge amount of data for processing and analysis. A significant portion of the transacted data between IoT devices is private information, which must not in any way be eavesdropped on or tampered with. Security in IoT devices is therefore of paramount importance for further development of the technology. Such devices typically have limited area and energy resources, which makes the use of classic cryptography prohibitively expensive. Physically Unclonable Functions (PUFs) are a class of novel hardware security primitives that promise a paradigm shift in many security applications; their relatively simple architecture can answer many of the security challenges of energy-constrained IoT devices. In this paper, we discuss the design challenges of secure IoT systems; then we explain the principles of PUFs; finally we discuss the outstanding reliability and security problems of PUF technology and outline the open research questions in this fiel
The effects of BTI aging on the susceptibility of on-chip communication schemes to soft errors in nano-scale CMOS technologies
No full textVLSI Design of ECG Monitor from Concept to Silicon
No full textThe proliferation of chronic diseases such as heart failure due to the aging population is causing an increasing pressure on healthcare systems; this makes it extremely difficult to maintain the quality of care for patients without significant increase of budget. Switching resources from crisis management by hospitalizing patients to health maintenance through home tele-monitoring is promising solution that can help achieve high quality of care at an affordable cost. To make this vision a reality, there is a strong need for portable diagnostic systems. Such devices are expected to battery operated and to communicate wirelessly, therefore they have stringent power consumption constraints. This work investigates the design and implementation of electrocardiogram monitor used for the detection and classification of the heart’s electrical signal. This device is an essential part of chronic heart failure diagnostic equipment and implantable pacemakers. The design process of such a system is described from initial specifications to final implementation and testing on field programmable gate array (FPGA). Power-saving methodologies employed at every stage of development are also presented
Teaching Hardware Security at Southampton University: A Course Design and Evaluation
No full textThis work describes the design and evaluation of a secure chip design module for graduate students and junior engineers with electronics and computer engineering. This course has two broad goals, the first is to teach students how design complex systems on chips using industry standard tools and the second is to educate them on emerging hardware security threats and countermeasures. The design principles of the course are explained in details, followed by a summary of the evaluation processed we have used and how they helped to improve the quality of our teaching and enhance students’ experience
The Analysis of the Implementation of Concurrent Error Detection in Multi-Level Flash Memories
No full textThe increasing demands for high density and low cost non-volatile storage media are driving the technology development of flash memories. A novel solution to increase its storage density and reduce its cost per bit is to adopt the Multilevel Cell technologies. This approach consists of storing several bits in one transistor. According to ITRS report in 2004 the number of bits which can be stored in one cell will be 8 in 2010. One disadvantage of this approach is the degradation in the memory reliability therefore an efficient testing method which has some error correction ability should be used for ML-flash memories in order to allow its use in reliable systems. This paper investigates the applicability and overheads of a concurrent testing technique based on symbol error correcting codes on multilevel flash memories. This method is explained and testing schemes of for 4, 16, 32, 64 level flash memories are described and simulated in VHDL. Area overheads and timing impact of this method are also discusse
Hardware-based security solutions for the Internet of Things using physical unclonable functions
No full textCourse on secure hardware design of silicon chips
Full text linkThis study describes the design and evaluation of a secure chip design module for graduate students and junior engineers with electronics and computer engineering. This course has two broad goals, the first is to teach students how design complex systems on chips using industry standard tools and the second is to educate them on emerging hardware security threats and countermeasures. There are a number of strategies currently been employed to handle the rising complexity of chip design, namely reuse, abstraction and automation. The authors aim to show how to employ these approaches to produce working systems within a time-constrained environment similar to that of IC design companies. One of the unique features of this module is its approach of treating hardware security as an integral part of the chip design process and as one of the design metrics which can be evaluated and optimised, this allows students to better understand the root causes of this issue and to think more constructively about potential countermeasures. The course is designed based on the principles of constructive alignment method and Kolb learning cycle. Detailed syllabus and assessment exercises are included. Feedback results from students' surveys indicate that the module has been positively received
Throughput Optimization for Area-Constrained Links With Crosstalk Avoidance Methods
No full textThe effect of crosstalk avoidance codes on the throughput of fixed width communication channels is studied. Closed form expressions of the throughput which incorporate the dimensions of the interconnects and the wiring overheads incurred by such techniques are derived for lines under different buffering conditions. These formulae are utilized to optimize the bandwidth of constrained-area parallel buses under different latency and power constraints. Our results are confirmed by the simulations we have performed in Spectre for a UMC CMOS 90-nm technology
- …
