273,519 research outputs found
Fabrication and characterisation of novel Ge MOSFETs
No full textAs high-k dielectrics are introduced into commercial Si CMOS (Complimentary Metal Oxide Semiconductor) microelectronics, the 40 year channel/dielectric partnership of Si/SiO2 is ended and the door opened for silicon to be replaced as the active channel material in MOSFETs (Metal Oxide Semiconductor Field Effect Transistor). Germanium is a good candidate as it has higher bulk carrier mobilities than silicon. In addition, Si and Ge form a thermodynamically stable SiGe alloy of any composition, allowing Ge to be implemented as a thin layer on the surface of a standard Si substrate. This thesis is a practical investigation on several aspects of Ge CMOS technology.
High-k dielectric Ge p-MOSFETs are electrically characterised. A large variation in interface state densities is demonstrated to be responsible for a threshold voltage shift and this is proportional to reciprocal peak mobility due to the Coulomb scattering of carriers by charged states. A theoretical mobility is fitted to that measured at 4.2 K and confirms that interface states are the main source of interface charged impurities.
The model demonstrates a reduction in the interface charged impurity density in p-MOSFETs that underwent a PMA (Post Metallisation Anneal) in hydrogen atmosphere and that the anneal also reduces the RMS (Root Mean Square) dielectric/semiconductor interface roughness, from an average of 0.60 nm to 0.48 nm.
High-k strained Ge p-MOSFETs are electrically characterised and have peak mobilities at 300 K (470 cm2 V-1 s-1) and 4.2 K (1780 cm2 V-1 s-1) far in excess of those measured for the unstrained Ge p-MOSFETs (285 cm2 V-1 s-1,785 cm2 V-1 s-1 respectively). Strained Ge n-MOSFETs perform significantly worse than standard Si P, - MOSFETs primarily due to a high source/drain resistance.
A 10 nm thick SiGe-01 (On Insulator) layer with a Ge composition of 58% is obtained from a 55 nm Si0_88Ge1o2. initial layer on 100 nm Si-Ol substrate via the germanium condensation technique. For the first time, germanium is demonstrated to diffuse through the BOX (Buried OXide) during Ge-condensation and into the underlying Si substrate. An order of magnitude increase in the calculated ITOX (Internal Thermal OXidation) rate of the BOX in the final stages of Ge-condensation is hypothesised to be responsible for stopping this diffusion
High quality Schottky contacts for limiting leakage currents in Ge-based Schottky barrier MOSFETs
No full textSchottky barrier (SB) Ge channel MOSFETs suffer from high drain-body leakage at the required elevated substrate doping concentrations to suppress source-drain leakage. Here we show that electrodeposited Ni-Ge and NiGe/Ge Schottky diodes on highly doped Ge show low off current, which might make them suitable for SB p-MOSFETs. The Schottky diodes showed rectification of up to 5 orders in magnitude. At low forward biases the overlap of the forward current density curves for the as deposited Ni/n-Ge and NiGe/n-Ge Schottky diodes indicates Fermi-level pinning in the Ge band gap. The SB height for electrons remains virtually constant at 0.52 eV (indicating a hole barrier height of 0.14 eV) under various annealing temperatures. The series resistance decreases with increasing annealing temperature in agreement with four point probe measurements indicating the lower specific resistance of NiGe as compared to Ni, which is crucial for high drive current in SB p-MOSFETs. We show by numerical simulation that by incorporating such high quality Schottky diodes in the source/drain of a Ge channel PMOS, highly doped substrate could be used to minimize the subthreshold source to drain leakage current
Electrodeposited Ni/Ge and germanide schottky barriers for nanoelectronics applications
No full textIn recent years metal/semiconductor Schottky barriers have found numerous applications in nanoelectronics. The work presented in this thesis focuses on the improvement of a few of the relevant devices using electrodeposition of metal on Ge for Schottky barrier fabrication. This low energy metallisation technique offers numerous advantages over the physical vapour deposition techniques. Electrical characteristics of the grown diodes show a high quality rectifying behaviour with extremely low leakage currents even on highly doped Ge. A non-Arrhenius behaviour of the temperature dependence is observed for the grown Ni/Ge diodes on lowly doped Ge that is explained by a spatial variation of the barrier heights. The inhomogeneity of the barrier hights is explained in line with an intrinsic surface states model for Ge. The understanding of the intrinsic surface states will help to create ohmic contacts for doped n-MOSFETs. NiGe were formed single phase by annealing. Results reveal that by using these high-quality germanide Schottky barriers as the source/drain, the subthreshold leakage currents of a Schottky barrier MOSFET could be minimised, in particular, due to the very low drain/body junction leakage current exhibited by the electrodeposited diodes. The Ni/Ge diodes on highly doped Ge show negative differential conductance at low temperature. This effect is attributed to the intervalley electron transfer in Ge conduction band to a low mobility valley. The results show experimentally that Schottky junctions could be used for hot electron injection in transferred-electron devices. A vertical Co/Ni/Si structure has been fabricated for spin injection and detection in Si. It is shown that the system functions electrically well although no magnetoresistance indicative of spin injection was observed
Transport properties for pure strained Ge quantum well
No full textModulation doped heterostructures consisting of a strained Ge (sGe) quantum well on a Si0.2Ge0.8 virtual substrate have been used to study enhancement of the transport properties of holes in the sGe channel due to the effective reduction of impurity scattering by placing the doping layer away from the channel.
Electrical and structural analysis was performed for sGe heterostructures produced with a range of growth parameters. The highest hole mobility was 1.34×106 cm2 /Vs at 0.5 K for a sGe quantum well in a 'normal' structure (i.e. doped above the channel) at a sheet density of 2.9×1011 cm-2, which is the largest hole mobility reported in Ge to date. 'Inverted' structures (doping layer under the channel) were also studied for different sample parameters such as channel thickness, spacer thickness, doping and different temperature growth, with a hole
mobility as high as 5.08×105 cm2 /Vs at a sheet density of 5.14×1011 cm-2 at 90 mK.
Simulations of the scattering limited mobility for inverted and normal structures were performed and showed that at low sheet density background impurity scattering limits the low temperature hole mobility. However, as the sheet density increases interface roughness scattering becomes the mobility limiting process, especially in the case of inverted structures where the resistivity and mobility anisotropy is more pronounced.
Magnetotransport measurements revealed the lowest reported effective mass for holes in Ge of 0.063±0.001 m0 for the normal structure and 0.07±0.002 m0 & 0.063±0.003 m0 for two inverted structures, and highest Dingle factors of α=78 and 33 for the normal and inverted structures, respectively. The low level of background impurities, high structural quality, and pure Ge channel revealed by structure characterisation are believed to be responsible for these exceptionally high values of mobility
Fe/Ge catalyzed carbon nanotube growth on HfO<sub>2</sub> for nano-sensor applications
No full textA carbon nanotube (CNT) growth process on HfO2 is reported for the first time for application in nano-sensors. The process uses a combination of Ge nanoparticles and ferric nitrate dispersion and achieves an increase in CNT density from 0.15 to 6.2 μm length/ μm2 compared with the use of ferric nitrate dispersion alone. The growth process is validated by the fabrication of back-gate CNT field-effect transistors (CNTFETs) using Al source/drain (S/D) contacts and a H2 anneal at 400 degrees C. The transistors exhibit p-FET behavior with an Ion/Ioff ratio of 105 and a steep sub-threshold slope of 130 mV/dec. These results are rather surprising, as earlier research in the literature on CNTFETs with Al S/D electrodes showed n-FET behavior. The p-FET behavior is shown to be due to the H2 anneal, which we ascribe to the smaller electron affinity of hydrogenised CNTs. Measurements of the temperature dependence of the drain current show low Schottky barrier height Al S/D contacts after a H2 anneal, which tends to confirm this explanation
Strain-relaxed, high Ge content, SiGe layers grown on Si (100) substrate by reduced pressure - chemical vapour deposition (RP-CVD)
No full textA different approach was taken to relieve strain from a high Germanium (Ge) content,
Silicon-Germanium (SiGe) layers on a Silicon (Si) (100) substrate by growing a thin Ge
under-layer between substrate and layer. The Ge under-layer acts as a strain reliving platform
for further growth of a high Ge content SiGe layer to improve the structural quality of the
sample by reducing the Root Mean Squared Roughness (RRMS) and threading dislocation density
(TDD).
The proposed structure involves the growth of thin Si0.3Ge0.7 and Si0.5Ge0.95 buffer layers of
an average thickness of 350 nm grown on a Si (100) substrate and their structural qualities
assessed. Experimental techniques include High Resolution X-Ray Diffraction, Atomic Force
Microscopy, Transmission Electron Microscopy, and Defect Etching. All samples were
shown to be fully relaxed and have a surface roughness between 1-8 nm. However, a
threading dislocation density of 109 cm-2 was witnessed. Although these results are the first of
their kind, further research into improving structural qualities is to be investigated in the
future
Ge-on-Si single-photon avalanche diode detectors: design, modeling, fabrication, and characterization at wavelengths 1310 and 1550 nm
No full textThe design, modeling, fabrication, and characterization of single-photon avalanche diode detectors with an epitaxial Ge absorption region grown directly on Si are presented. At 100 K, a single-photon detection efficiency of 4% at 1310 nm wavelength was measured with a dark count rate of ~ 6 megacounts/s, resulting in the lowest reported noise-equivalent power for a Ge-on-Si single-photon avalanche diode detector (1×10-14 WHz-1/2). The first report of 1550 nm wavelength detection efficiency measurements with such a device is presented. A jitter of 300 ps was measured, and preliminary tests on after-pulsing showed only a small increase (a factor of 2) in the normalized dark count rate when the gating frequency was increased from 1 kHz to 1 MHz. These initial results suggest that optimized devices integrated on Si substrates could potentially provide performance comparable to or better than that of many commercially available discrete technologies
Laser-vibrometric ultrasonic characterization of resonant modes and quality factors of Ge membranes
No full textThe vibrations of a single-crystal germanium (Ge) membrane are studied in air and vacuum using laser vibrometry, in order to determine mechanical properties such as Q-factors, tensile stress, anisotropy, and robustness to shock. Resonance modes up to 3:2 are identified, giving a residual stress measurement of 0.22 GPa, consistent with the value obtained from x-ray relaxation studies. The membrane is found to be isotropic, with Q-factors ranging from around 40 at atmospheric pressure to over 3200 at 5 x 10-4 mbar, significantly lower than those found in polycrystalline Ge micromechanical devices. The robustness to shock is explained through the high resonance mode frequencies and the dissipation mechanism into the substrate, which is a direct consequence of having a high quality film with low residual tensile stress, giving the potential for such films to be used in optoelectronic devices
Mechanism of vertical Ge nanowire nucleation on Si (111) during subeutectic annealing and growth
No full textThe direct integration of Ge nanowires with silicon is of interest in multiple applications. In this work, we describe the growth of high-quality, vertically oriented Ge nanowires on Si (111) substrates utilizing a completely sub-Au-Si-eutectic annealing and growth procedure. With all other conditions remaining identical, annealing below the Au-Si eutectic results in successful heteroepitaxial nucleation and growth of Ge nanowires on Si substrate while annealing above the Au-Si eutectic leads to randomly oriented growth. A model is presented to elucidate the effect of the annealing temperature, in which we hypothesized that sub-Au-Si-eutectic annealing leads to the formation of a single and well-oriented interface, essential to template heteroepitaxial nucleation. These results are critically dependent on substrate preparation and lead to the creation of integrated nanowire systems with a low thermal budget process
Novel nonalloyed thermally stable Pd/Sn and Pd/Sn/Au ohmic contacts for the fabrication of GaAs MESFETs
No full textGaAs metal-semiconductor field-effect transistors (MESFETs) have been fabricated utilizing thermally stable Pd/Sn and Pd/Sn/Au ohmic contacts for the first time. MESFETs with Pd/Ge ohmic contacts are fabricated for comparison. The thermal stability of the Pd/Sn, Pd/Ge and Pd/Sn/Au ohmic contacts is also presente
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