103,536 research outputs found
Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics
No full textGate capacitance of metal-oxide-semiconductor devices with ultra-thin high-K gate-dielectric materials is calculated taking into account the penetration of wave functions into the gate-dielectric. When penetration effects are neglected, the gate capacitance is independent of the dielectric material for a given equivalent oxide thickness (EOT). Our selfconsistent numerical results show that in the presence of wave function penetration, even for the same EOT, gate capacitance depends on the gate-dielectric material. Calculated gate capacitance is higher for materials with lower conduction band offsets with silicon. We have investigated the effects of substrate doping density on the relative error in gate capacitance due to neglecting wave function penetration. It is found that the error decreases with increasing doping density. We also show that accurate calculation of the gate capacitance including wave function penetration is not critically dependent on the value of the electron effective mass in the gate-dielectric region
Gate recess engineering of pseudomorphic In0.30GaAs/GaAs HEMTs
No full textThe authors report how the performance of 0.12 μm GaAs pHEMTs is improved by controlling both the gate recess width, using selective dry etching, and the gate position in the source drain gap, using electron beam lithography. pHEMTs with a transconductance of 600 mS/mm, off state breakdown voltages >2 V, fτ of 120 GHz, f max of 180 GHz and MAG of 13.5 dB at 60 GHz are reported
Suspended Gate Silicon Nanodots memory
No full textThis paper proposes a new non-volatile semiconductor memory which features a suspended gate integrated with silicon nanocrystals dots as a floating gate and the MOSFET as a readout. Performing three-dimensional finite element simulations combined with an analytical plate-capacitor model, we clarify the pull-in/pull-out operation of the suspended gate. We also show the dependence of the hysteresis cycle characteristics on material and structural parameters
Modeling of direct tunneling gate current and gate capacitance in deep submicron MOSFETs with high-K dielectric.
No full textScaling down of MOS device dimensions is accompanied by a decrease in gate-oxide thickness and an increase in substrate doping density. When gate oxide thickness becomes less than 2 nm, a substantial current follows through gate-oxide due to direct tunneling. In order to reduce this current, International Technology Roadmap for Semiconductors (ITRS) has suggested replacement of SiO2 gate insulator layer by high-K dielectrics. For a given equivalent oxide thickness (EOT), high-K dielectrics offer greater physical thickness. The direct tunneling (DT) current and the gate capacitance for an inverted n-MOS device with different dielectrics used as gate insulator is studied. Coupled Schrodinger’s and Poisson’s equations are solved self-consistently. Open boundary conditions, taking account the wavefunction tail inside the gate dielectric within the self-consistent loop are used to solve Schrodinger’s equation. DT current increases exponentially with the decrease of conduction band offset for electrons travelling from silicon substrate to dielectric. As general trend of dielectrics is to decrease of conduction band offset with the increase of dielectric constant, use of high-K material as gate insulator results in prominent influence of direct tunneling of carriers on potential profile. Therefore in DT current calculation effect of wavefunction penetration on potential profile is incorporated within self-consistent loop. Results of this simulation is compared with published experimental results and also with the results of the simulation where penetration effect on potential profile is neglected. Results show that neglect of wavefunction penetration effect on potential profile causes underestimation of DT current. A comprehensive analysis of the effect of wavefunction penetration on the gate capacitance of the MOSFETs with high-K dielectrics is also done. Gate capacitance from conventional modeling is found to be independent of dielectric materials for a given EOT. The study reveals that accounting for wavefunction penetration into the gate dielectric causes gate capacitance to vary from material to material for a given EOT. Consequently wavefunction penetration effects must be considered to determine properties of future generation devices where high-K dielectrics will be employed as gate insulator
Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance
No full textThe vertical MOSFET structure is one of the solutions for reducing the channel length of transistors under 50nm. Surround gates can be easily realised in vertical MOSFETs which offer increased channel width per unit silicon area. In this paper, a low overlap capacitance, surround gate, vertical MOSFET technology is presented. A new process that uses spacer or fillet local oxidation is developed to reduce the overlap capacitance between the gate and the source/drain electrodes. Electrical characteristics of surround gate n-MOSFETs are presented and compared with characteristics from single gate and double gate devices on the same wafer. Transistors with channel length down to 100nm have been realised. They show good symmetry between the source on top and source on bottom configuration and subthreshold slope down to 100mV. The short channel effects of the surround gate MOSFETs are investigated
Gate Capacitance of deep submicron MOSFETS with high-K gate dielectrics
No full textWe study gate capacitance of deep submicron MOSFETs with high-K gate dielectrics. Schrödinger’s equation is solved by applying an open boundary condition at silicon-gate dielectric interface. Self-consistent numerical results reveal that accounting for wave function penetration into the gate dielectric causes the carrier distribution to be shifted closer to the gate dielectric. This effect increases with increasing gate voltage and also increases with the decreasing conduction band offset of the gate dielectric material with silicon. Gate capacitance calculated from conventional modeling is found to be independent of dielectric materials for a given equivalent oxide thickness (EOT). But our study shows that when wave function penetration into the gate dielectric is considered, gate capacitance for a given EOT increases with a decrease in the conduction band offset. Effects of substrate doping density on gate capacitance are found to be negligible when wave function penetration effects are incorporated
Performance enhancements in scaled strained-SiGe pMOSFETs with HfSiOx/TiSiN gate stacks
No full textThe short-channel performance of compressively strained Si0.77Ge0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe
Effects of neglecting carrier tunneling on electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs
No full textWe investigate the validity of the assumption of neglecting carrier tunneling effects on self-consistent electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs. Comparison between simulated and experimental results shows that for accurate modeling of direct tunneling current, tunneling effects on potential profile need to be considered. The relative error in gate current due to neglecting carrier tunneling is higher at higher gate voltages and increases with decreasing oxide thickness. We also study the direct tunneling gate current in MOSFETs with high- gate dielectrics
Improved self-gain in deep submicrometer strained silicon-germanium pMOSFETs with HfSiOx/TiSiN gate stacks
No full textThe self-gain of surface channel compressively strained SiGe pMOSFETs with HfSiOx/TiSiN gate stacks is investigated for a range of gate lengths down to 55 nm. There is 125% and 700% enhancement in the self-gain of SiGe pMOSFETs compared with the Si control at 100 nm and 55 nm lithographic gate lengths, respectively. This improvement in the self-gain of the SiGe devices is due to 80% hole mobility enhancement compared with the Si control and improved electrostatic integrity in the SiGe devices due to less boron diffusion into the channel. At 55 nm gate length, the SiGe pMOSFETs show 50% less drain induced barrier lowering compared with the Si control devices. Electrical measurements show that the SiGe devices have larger effective channel lengths. It is shown that the enhancement in the self-gain of the SiGe devices compared with the Si control increases as the gate length is reduced thereby making SiGe pMOSFETs with HfSiOx/TiSiN gate stacks an excellent candidate for analog/mixed-signal applications
Improved sub-threshold Slope in RF vertical MOSFETS using a frame gate architecture
No full textWe report a CMOS-compatible vertical MOSFET, which incorporates a frame gate architecture suitable for application in RF circuits. Fabricated surround gate vertical MOSFETs with the frame gate architecture show no degradation of short channel effects when the channel length is scaled, while control devices show significantly degraded sub-threshold slope and DIBL. The frame gate vertical MOSFETs show near ideal sub-threshold slopes of 70-80mV/decade and DIBL of 30-35mV/V in a 100 nm gate length nMOS device. In contrast, the control vertical MOSFETs without the frame gate exhibit sub-threshold slopes of 110 to 140 mV/decade and DIBL of 100 to 280 mV/V. This improved sub-threshold slope is explained by the elimination of etch damage during gate etch
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