1,721,018 research outputs found
The role of sub-interpolation for Delay-Line Time-to-Digital Converters in FPGA devices
No full textMost of the Time-to-Digital Converters (TDCs) implemented in Field Programmable Gate Array (FPGA) devices are based on Tapped Delay Lines (TDLs). This solution makes mandatory the implementation of sub-interpolation procedures in the processing flow in order to mitigate effects of the different characteristics of the FPGA resources used Specifically, we focus issues of the sub-interpolation topic also still outstanding and realize the experimental comparison of the state-of-art techniques, providing design rules for their optimal implementation. According to the host electronic device, the paper reveals the design rules to get the best performance, by using known sub-interpolation techniques but introducing criteria of choice and design procedures never presented in literature. These are fundamental for the most proper and useful application of sub-interpolation techniques in designing high-performance TDCs
Time-to-Digital Converter IP-Core for FPGA at State of the Art
Full text linkThe Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time-Mode (TM) circuits almost unfeasible. In particular, in Programmable Logic (PL) devices, such as FPGAs, the operation of the logic is usually synchronous with the system clock. However, it can happen that a very high-performance specifications demands to abandon this paradigm and to follow an asynchronous implementative solution. The main driver forcing the use of programmable logic solutions instead of tailored Application Specific Integrated Circuits (ASIC), best suiting an asynchronous design, is the request coming from the research community and industrial RD of fast-prototyping at low Non Recursive Engineering (NRE) costs. For instance in the case of a high-resolved Time-to-Digital Converter (TDC), a signal clocked at some hundreds of MHz implemented in FPGA allows implementing a TDC with resolution at ns. If a higher resolution is required, the signal frequency cannot be increased further and one of the aces up the designer's sleeve is the propagation delay of the logic in order to quantize the time intervals by means of a so-called Tapped Delay-Line (TDL). This implementation of TDL-based TDC in FPGAs requires special attention by the designer both in making the best use of all available resources and in foreseeing how signals propagate inside these devices. In this paper, we investigate the implementation of a high-performance TDL-TDC addressed to 28-nm 7-Series Xilinx FPGA, taking into account the comparison between different technological nodes from 65-nm to 20-nm. In this context, the term high-performance means extended dynamic-range (up to 10.3 s), high-resolution and single-shot precision (up to 366 fs and 12 ps r.m.s respectively), low differential and integral non-linearity (up to 250 fs and 2.5 ps respectively), and multi-channel capability (up to 16)
Digital Instrument for Time Measurements: Small, Portable, High-Performance, Fully Programmable
Full text linkWe present a small, portable, plug-and-play time measurement instrument entirely based on Field Programmable Gate Array (FPGA). Its performance is state-of-the-art in terms of the most recent Application-Specific Integrated Circuit (ASIC) solutions of Time-to-Digital Converters (TDCs), and all operating features are fully-programmable. The instrument offers an excellent cost-performance and is suitable for detector test and time correlation measurement applications. More generally, the instrument is very well suited for fast-prototyping of systems where time measures are involved, at low cost and design effort. All the features of the instrument can be easily accessed through either the Graphical User Interface (GUI) or directly from the software Application Programming Interface (API)
Cross-Talk Issues in Time Measurements
Full text linkThe enormous diffusion of Time-Mode circuits, in particular Time-to-Digital Converter (TDC) time measurement circuits, and at the same time the dizzying increase in parallel channels required by the most recent applications, for example in the automotive and digital imaging fields, brings the problem of electromagnetic interference between channels ever more to the fore. This phenomenon, generally known as Cross-Talk (XT), is particularly critical given the increase in the operating frequency and density of systems components, and its effect on the timing parameters in TDC measurements is investigated. Considering the time measurements, XT creates temporal shift on the physical events from which the timestamps are extracted; in this manner, an error in the measurements is generated. In order to detect the XT phenomena, a methodical analysis based on Code-Density Test (CDT) is performed; in this terms, two different typologies of XTs are investigated, which are correlated and uncorrelated XT. Furthermore, a TDC board is used as case study and all the XT sources are detected and classified. Thus, a classification of the importance of the different sources of XT is achieved and a solution to minimize the different causes is proposed
All-Digital Fully-Configurable Instrument for Multi-Channel Time Measurements at High Performance
No full textIn the contribution ′′Fully Programmable System for Multi-Channel Experiments Targeting to Time Measurement at High Performance′′ presented at 2017 Nuclear Science Symposium, we introduced a new instrument for time measurements in a prototype version. In this contribution we present the evolution of this instrument in its firmware and software parts, aimed at obtaining a processing architecture flexible, modular and migratable among different host devices.Main feature of the system is the multi-channel operating mode, up to 16 parallel inputs at maximum rate of 45 MHz per channel, with resolution of 250 fs and single channel precision below 12 ps r.m.s., over hardware full-scale range of 10.3 s extendable to some days simply via software.Time measures are performed by a Time-to-Digital Converter (TDC) structured as IP-Core compatible with Xilinx Field Programmable Gate Arrays (FPGAs) and Systems-on-Chips (SoCs) of last generation (28-nm 7-Series, 20-nm UltraScale, and 16-nm UltraScale+). The firmware composed of IP-Cores is more flexible with respect to a standard Hardware Description Language (HDL) code and allows the user inserting custom modules for adapting the instrument to specific purposes without putting at risk the performance of the TDC.Moreover, the most important feature of this organization in IP-Cores is that the firmware can be hosted in different FPGA/SoC modules, guaranteeing not only firmware and software, but also hardware re-configurability of the instrument
Digital instrument with configurable hardware and firmware for multi-channel time measures
Full text linkA new digital instrument for timing of events is presented. It is based on a reconfigurable, high-performance, 16-channel time-to-digital converter implemented in a Xilinx 7 Series 28-nm field programmable gate array device. Each channel provides timestamps with a least significant bit of 2 ps that states the resolution, whereas instead the single-shot precision is below 12.5 ps rms with the possibility of multihit measures at the maximum rate of 20 MHz. The default width of the full-scale range is 157 μs that can be extended at users choosing up to 15 days by means of proper time tagging procedures made available. The instrument achieves performance in terms of precision, resolution, and full-scale range of measurement at the state-of-art of existing solutions. The novelty is that besides performance, the presented instrument is totally reconfigurable by the user both in the hardware and in the firmware parts. Moreover, novel techniques of event acquisition (e.g., level-zero trigger) are introduced. These further features are not present in any other instrument available nor in the literature or in commerce and constitute a difference with respect to all referenced instruments
Synchronization in Networks of Time-to-Digital Converters based on Field Programmable Gate Arrays
No full textNowadays, in many high technological fields of research the classical Time-to-Digital-Converter (TDC) structure is no more satisfactory, since the architecture of one measuring unit connected to many sensors is no more feasible because the not sufficient number of channels, the lack of flexibility or both. This is the case, for instance, of Positron Emission Tomography (PET) facilities of last generation.In the Nuclear Science Symposium 2018 we presented a "All-Digital Fully-Configurable Instrument for Multi-Channel Time Measurements at High Performance". The present contribution deals with the implementation of a distributed architecture of TDCs, i.e. an instrument that allows measuring timestamps on different devices but with the same relative time reference. This allows managing measures performed by different TDCs like if they were collected by a unique device, so providing a huge flexibility that opens the way for new advanced applications like PET network detectors.The realization of a network for TDCs poses two main issues: a high-performance data transfer mechanism in addition to a precise and reliable synchronization methodology. This contribution focuses on the latter issue that is the most critical and complex to address. The analysis is carried out both from theoretical and implementation point of view
Hardware Description Language Phase-Locked Loop (HDL-PLL) Open Architecture for FPGAs
No full textThis contribution aims to be a proof of the feasibility of a fully open architecture in Hardware Description Language of a Phase-Locked Loop (HDL-PLL) implemented in Field Programmable Gate Array (FPGA).Main parts of the system are the Phase-Frequency Detector (PFD) based on a Time-to-Digital Converter (TDC) and the Digital-Controlled Oscillator (DCO).Both of them are implemented by means of asynchronous architectures making possible to tune the DCO output period, by means of a feedback loop, with resolution of 78 ps and cycle-cycle jitter below 75.3 ps r.m.s.The dynamic range of the HDL-PLL is set by the user during the implementation and varies from several hundreds of MHz with no practical lower limit
Complete System-on-Chip Linux-based Platform for Measurement and Generation of Time Domain Signals
No full textIn this contribution we present a novel implementation of a bundle hardware, firmware and software for the measurement and generation of time domain signals, based on a custom System-on-Chip Linux-based platform. Recently, many solutions have been already proposed both by the industry and by the academia for the measurement and generation of time events, in the forms of full-custom Application-Specific Integrated Circuits and Field Programmable Gate Array IP-Cores. However, while these solutions have proven themselves mostly satisfying in terms of performance, they often lack ease of use, upgrade and interfacing. Indeed, while those implementations are flexible and can be fully customized, integrating them in existing systems is usually, if not always, challenging. To solve these issues, we present here a hybrid hardware and software implementation of Time-to-Digital Converters and Digital-to-Time Converters in Programmable Logic. The main feature is the simplified, yet efficient, interface to other user logic or to the ARM core in the Xilinx Zynq-7000 System-on-Chips, which hosts a Linux-based Operating System. The interfacing of the two worlds is eased by a set of IP-Cores and libraries, so that the performance of the Programmable Logic part can be used and connected easily with the more flexible and user-friendly Processing System. This opens new opportunities, like the use of the Linux Operating System for simple transfer of data through advanced interfaces and protocols, without requiring complex hardware on the Programmable Logic part
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