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Hybrid circuit analysis of a suspended-gate silicon nanodot memory (SGSNM) cell
No full textWe report a hybrid numerical analysis of the suspended gate silicon nanodot memory (SGSNM) which co-integrates nano-electromechanical systems (NEMS) with silicon MOSFET technology. We propose a new hybrid equivalent circuit model for the SGSNM, in which a parallel-connected variable gate capacitance and variable tunnel resistance model the suspended gate pull-in/pull-out operation and the electron tunnelling process through the tunnelling oxide layer. The signals for the programming, erasing and reading processes are successfully achieved in the circuit level simulation. The programming/erasing speed is found 2.5 ns which is a combination between the mechanical SG pull-in (0.8 ns) and the tunnelling process (1.7 ns). Those characteristics and the fact that the SGSNM does not use exotic materials but Si-based materials, makes the SGSNM a serious candidate for non-volatile random access memory applications
Suspended Gate Silicon Nanodot Memory
No full textThe non-volatile memory market has been driven by Flash memory since its invention more than three decades ago. Today, this non-volatile memory is used in a wide variety of devices and systems from pen drives, mp3 players to cars, planes and satellites. However,the conventional floating gate memory technology in use for flash memory is facing a serious scalability issue, the tunnel oxide thickness cannot be reduced to less than 7nm as pointed out in the latest international technology roadmap for semiconductors (ITRS2010) [1]. The limit imposed on the tunnel oxide layer reduces the programming and erasing times, the scalability and endurance among other parameters. To overcome those inherent issues, this research is focused on the co-integration of nano-electromechanical systems (NEMS) with metal-oxide-semiconductor (MOS) technology in order to generate a new non-volatile and high speed memory. The memory device that we are proposing is a high-speed non-volatile memory structure called the Suspended Gate Silicon Nanodot Memory (SGSNM) cell. This non-volatile memory device features a MOSFET as a readout element, a silicon nanodot (SiNDs) monolayer as the floating gate and a movable suspended control gate isolated from the floating gate by an oxide layer and by an air-gap. The fundamental component in this novel device is the introduction of a doubly-clamped beam as a movable control gate, in which through this element, the programming and erasing operations take place. To understand the behaviour of the doubly-clamped beam structure, it is analysed by using analytical models such as the doubly-plate capacitor model and also by using two- and three-dimensional (2D and 3D) finite element method (FEM) analysis. The programming and erasing operations within the SGSNM occur when the suspended control gate is in contact with the tunnel oxide layer. This is the point at which the quantum-mechanical tunnelling mechanism (Fowler-Nordheim) takes place. Through this mechanism, the electrons are allowed to tunnel from the suspended control gate into the memory node and vice versa as a function of the applied voltage (bias). The tunnelling process is numerically analysed by implementing the Tsu-Esaki equation and the transfer matrix method within a homemade program which calculates the current density as a function of the tunnel oxide material and thickness. Both the suspended control gate and tunnelling process are implemented as analog behavioural models within the SGSNM cell that is simulated by using a commercial circuit simulator. From a transient analysis of the suspended control gate, it was found that the suspended control gate takes 0.8 nsec in pull-in on the tunnel oxide layer for a 1 ?m-long doubly-clamped structure. In contrast, the time that the memory node takes in charge and discharge is 1.7 nsec. Hence, the programming and erasing times are a combination between the mechanical pull-in and the charging time, which is 2.5 nsec due the fact that to both operations are symmetrical. Moreover, the suspended control gate was successfully fabricated and suspended. This process was performed by depositing a thin layer of aluminium (500 nm) over the sacrificial layer (poly-Si) by using an e-beam evaporator, which was patterned with doubly-clamped beam features through the photolithographic process. By using a combination of wet and dry etching processes, the aluminium and the sacrificial layer were successfully removed without affecting the substrate (Si-based) or the suspended control gate beam. In addition, Capacitance - Voltage measurements were performed on a set of doubly-clamped beams from which the pull-in effect was successfully obtained. Finally, the footprints for the memory device fabrication process were developed and sketched within the document as well as the design of three photomask
Suspended Gate Silicon Nanodots memory
No full textThis paper proposes a new non-volatile semiconductor memory which features a suspended gate integrated with silicon nanocrystals dots as a floating gate and the MOSFET as a readout. Performing three-dimensional finite element simulations combined with an analytical plate-capacitor model, we clarify the pull-in/pull-out operation of the suspended gate. We also show the dependence of the hysteresis cycle characteristics on material and structural parameters
Hybrid Numerical Analysis of a high-speed non-volatile Suspended Gate Silicon Nanodot Memory
No full textWe present a hybrid numerical analysis of a high-speed and non-volatile suspended gate silicon nanodot memory (SGSNM) which co-integrates a nano-electromechanical (NEM) control gate with a MOSFET as a readout element and silicon nanodots as a floating gate. A hybrid NEM-MOS circuit simulation is developed by taking account of the pull-in/pull-out operation of the suspended gate and electron tunnelling processes through the tunnel oxide layer as behavioural models. The signals for programming, erasing and reading are successfully achieved at circuit level simulation. The programming and erasing times are found as short as 2.5 nsec for a SGSNM with a 1-?m-long suspended gate, which is a summation of the mechanical pull-in/pull-out times and the tunnel charging/discharging times
Fabrication and characterisation of a double-clamped beam structure as a control gate for a high-speed non-volatile memory device
No full textWe report the fabrication and characterisation of a suspended double-clamped beam structure that is implemented as a movable control gate within a hybrid high-speed non-volatile memory device. This structure features a foundation of SiO2/Si layers over which a poly-Si layer (sacrificial) is deposited by using a low-pressure chemical vapour deposition (LPCVD) and as a movable control gate, an aluminium (Al) layer is deposited by using an e-beam evaporator. The Al layer is patterned with double-clamped beam structures by using photolithography and through a combination of wet and dry etching processes, the structures are successfully suspended and characterised by using a C–V meter. From the structure characterisation, the pull-in curve is successfully obtained and due to unexpected large short-range forces such as the van der Waals forces, the pull-out curve is not observed. In order to clarify this issue, a numerical analysis is performed in which the structural materials under test shown the influence of such short-range forces on the structure and a solution to override them is propose
NEMS-MOS and NEMS-SET hybrid functional systems for advanced information processing and extreme sensing
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