1,721,167 research outputs found
THE DEVELOPMENT OF A DIGITAL IN-LINE HOLOGRAPHY SYSTEM FOR THE APPLICATION IN HOLOGRAPHIC PARTICLE IMAGE VELOCIMETRY
No full textMaster'sMASTER OF SCIENCEDissertation Supervisors: 1. Associate Professor George Barbastathis, MIT. 2. Assistant Professor Gan Chee Lip, SMA Fellow, NT
IMD TDDB (TIME DEPENDENCE DIELECTRIC BREAKDOWN) ON LOW-k DIELETRICS
No full textMaster'sMASTER OF SCIENCE IN ADVANCED MATERIALS FOR MICRO- & NANO- SYSTEMS1. Ass. Prof. Gan Chee Lip, SMA Fellow, NTU. 2. Dr. Galor Zhang, Principal Engineer, Chartered Semiconductor Manufacturing Co
0.35 MICROMETER EEPROM SHRINK CELL QUALIFICATION
No full textMaster'sMASTER OF SCIENCE IN ADVANCED MATERIALS FOR MICRO- & NANO- SYSTEMSDissertation Supervisors: 1. Assistant Professor Gan Chee Lip, NTU. 2. Mr.Li Weining, Chartered. 3. Mr. Li Zhaobing, Chartere
SIMULATION OF COPPER ELECTRODEPOSITION FOR HIGH ASPECT RATIO THROUGH- SILICON VIA APPLICATIONS IN THREE- DIMENSIONAL INTEGRATED CIRCUITS
No full textMaster'sMASTER OF SCIENCE IN ADVANCED MATERIALS FOR MICRO- & NANO- SYSTEMSSupervisors: 1. Asst. Prof. Gan Chee Lip, School of MSE, NTU. 2. Dr. Hongyu Li, SPT, Institute of Microelectronics (IME)
CHARACTERIZATION OF POWERMOSFET
No full textMaster'sMASTER OF SCIENCE IN ADVANCED MATERIALS FOR MICRO- & NANO- SYSTEMSDissertation Supervisors: 1. Assistant Professor Gan Chee Lip, NTU. 2. Mr. Teo Yeow Meng, Chartered. 3. Mr. Kim Hung Jin, Chartere
C015 YIELD IMPROVEMENT
No full textMaster'sMASTER OF SCIENCE IN ADVANCED MATERIALS FOR MICRO- & NANO- SYSTEMSDissertation Supervisors: 1. Au Hing Ho, Principal Engineer, SSMC. 2. Asst Prof Gan Chee Lip, SMA Fellow, NT
Impact of deposition conditions on the crystallization kinetics of amorphous GeTe films
Get PDFThe speed at which phase change memory devices can operate depends strongly on the crystallization kinetics of the amorphous phase. To better understand factors that affect the crystallization rate, we have investigated crystallization of GeTe films as a function of their deposition temperatures and deposition rates, using X-ray synchrotron radiation and Raman spectroscopy. As-deposited films were found to be fully amorphous under all conditions, even though films deposited at higher temperatures and lower rates experienced lower effective quench rates. Non-isothermal transformation curves show that the apparent crystallization temperature of GeTe films decreases with increasing deposition temperature and decreasing deposition rate. It was found that this correlates with a decrease in the activation energy for nucleation (calculated using Kissinger’s analysis), while the activation energy for crystal growth remained unaffected. From Raman spectroscopy measurements, it was found that increasing the deposition temperature or decreasing the deposition rate, and therefore the effective quench rate, reduces the number of homopolar Te–Te bonds and thereby reduces the barrier to crystal nucleation.Singapore-MIT Alliance for Research and Technology (SMART
Fabrication of ordered anodic alumina oxide for imprinting templates
No full textPorous Anodic Aluminum Oxide (AAO) has been widely known for its ability to form hexagonally packed nanostructured arrays. AAO assisted approach also provides many advantages over conventional lithographic techniques for the fabrication of simple sub-100 nm nanostructure arrays. Nanostructured arrays fabricated on surfaces have wide range of potential applications in areas such as micro and nanoelectronics, photoelectronics, information storage, sensing, etc.
In this project, soft-imprinting method by using Reactive Ion Etching (RIE) to transfer the hexagonal arrays pattern of the AAO mask onto another substrate will be demonstrated. First of all, the method to fabricate free standing AAO mask will be proposed. The term free standing here refers to mechanically reinforced AAO templates (e.g. using PMMA coating as the mechanical support) so that large areas of very thin layer AAO templates (< 1 μm) could be fabricated and easily handled during the process.
Next, soft imprinting method on SiO2 substrates by RIE using a free-standing AAO mask will be proposed and demonstrated. Removal of PMMA coating before the RIE was critical, so two methods of PMMA removal will be studied in this project. The main focus of this project was to study the feasibility of transferring the hexagonal array pattern from the AAO mask onto the SiO2 substrate.Bachelor of Engineering (Materials Engineering
Cu metallization and dielectric removal for failure analysis of ICs
No full textAlthough a defect may be well understood electrically in the recent years, capturing the anomaly into image remains necessary to verify the defect location. As technology further develops, ICs nowadays have more than one interconnect layer. Hence, it is necessary to first remove the overlying layers, otherwise viewing of the embedded defects would be impossible. However, in some cases, the removal of one layer can act as an in-situ decoration of another layer, masking the defect or removing the defect. Thus, it is important that the delayering (also known as parallel lapping) method only removes the unwanted layer.
The main focus of this project is to study the side effect of deprocessing technique for 65 nm copper chip focusing on polishing methodology.
There are two known issues with polishing and they are, inability to achieve a 100% success rate and edge effects which affect the overall planarity of the sample. Edge effect can be caused by several factors such as long polishing times, excessive application of pressure or force, improper usage of slurry with wrong type of polishing cloth, sample is being lowered too much into the polishing cloth.
In the experiments, the polisher was set with two different polishing modes which include oscillation with rotation and oscillation only. The purpose is to find out which of the mode would give a lesser edge effect. Moreover, the effect of the polishing duration and force applied on the sample during polishing as well as the introduction of sacrificial layers will be investigated.
Optical images of the Cu chip were captured during the delayering process and FIB was also used to quantify the thicknesses of the layer stacks for analysis. After analyzing the results obtained from the experiments, it was found that polishing the sample with oscillation mode only and adding sacrificial to samples do help in minimizing edge effect at long polishing times.Bachelor of Engineering (Materials Engineering
Study on low temperature indium based solder for 3D integrated circuits application
No full textDue to limitations of the conventional 2-dimensional integrated circuit (IC) layout, the electronics industry has shifted its research focus towards 3-dimensional (3D) ICs design to overcome such future problems. A common 3D ICs architecture that has been proposed involves the stacking of multiple chips that are bonded inter-facially using solders at low temperatures and pressure. As recent international regulations have prohibited the use of established lead based solder technology (which is toxic), a suitable replacement solder material needs to be found.
The purpose of this study is to investigate the viability of an Indium-based solder alloy for 3D IC chip stacking and bonding purpose. In this study, 75In25Sn solder is bonded at 1.9MPa while the bonding and annealing temperature and varied in the range between room temperature to 200°C. From the results obtained, the bonding mechanism is proposed. Bonding at higher temperatures would result in higher true contact area between the solder and the copper surface. Through annealing at higher temperatures, inter-metallic compounds (IMC) would form from these contact sites.
To understand the kinetics of IMC formation, a simple in-situ experiment was carried out using solder and copper layers that were sputtered onto a glass slide. The proposed experiment hopes to reduce the time required by conventional study methods. However, further work is required as the final results achieved were not within expected theoretical data.
This study concludes that indium based alloy is a suitable candidate as a solder material for 3D ICs. Its low melting point and ability for good IMC formation allows for bonding at low pressure and temperatures. Further studies could be done to understand the impact of varying bonding pressure and other composition ratios.Bachelor of Engineering (Materials Engineering
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