1,720,965 research outputs found
Analysis and Design of mm-Wave Frequency Dividers Based on Dynamic Latches With Load Modulation
Full text linkThe availability of wide-band low-power frequency dividers is fundamental in transceivers for emerging mm-wave applications. Up to date injection locked topologies have been investigated for very high frequency operations but at the price of large area and limited frequency range. In this work, we investigate a new class based on dynamic latches with load modulation. The proposed latches can be viewed as the evolution of classic static CML latches where the regenerative cross-coupled pair is removed for minimum parasitic at output nodes, i.e., maximum speed, and loads are modulated by the input clock for maximum charge retention during hold times. A time-domain circuit inspection aimed at deriving analytical expressions for maximum and minimum operation frequency and providing guidelines for optimum design is reported. Prototypes of dividers by 4, realized in 32 nm bulk CMOS, operate between 14 GHz and 70 GHz, demonstrating a fractional bandwidth in excess of 60% in the entire range, 4.8 mW of maximum power consumption and 55 ×18 μm2 occupied area
A 5mW CMOS wideband mm-wave front-end featuring 17dB of conversion gain and 6.5 dB minimum NF
No full textThe low quality factor of passive components at mm-wave limits the impedance magnitude of resonators and leads to poor current to voltage conversion in amplifiers. To achieve significant LNA gain at mm-wave, multiple stages are required with the consequence of large power dissipation. Delaying the current to voltage conversion at intermediate frequency while processing the mm-wave signal in current domain is pursued in this work. LNA and mixer are merged in a single stage and show an overall front-end noise figure comparable to state of the art CMOS stand-alone LNAs. In view of integration of large phased arrays for wireless data transfers at Gbit/s, the solution offers the key advantage of an extremely low power consumption together with a very low occupied area. Test chips realized in 65nm CMOS, show the following performances: 48GHz to 62GHz input frequency range, conversion gain of 17dB and minimum noise figure of 6.5dB when translating the signal to an intermediate frequency of 18.5GHz. Power dissipation and die area are 5mW and 320 x 170 m2 only. Normalizing performances by means of the usually adopted figure of merit for LNAs, the proposed front-end outperforms all recently published CMOS LNAs while providing both amplification and frequency translation
A 4.8mW inductorless CMOS Frequency Divider-by-4 with more than 60% Fractional Bandwidth up to 70GHz
No full textFrequency synthesizers at mm-waves would benefit from wide-band low-power dividers with large division factors. This work proposes a divider-by-4 based on clocked differential amplifiers working as dynamic CML latches. The clock modulates both the tail current and the load resistance of the differential pair, allowing a wide locking range. Prototypes, realized in 32nm CMOS, operate between 14GHz and 70GHz demonstrating a fractional bandwidth in excess of 60% in the entire range, 4.8mW of maximum power consumption and 55x18μm2 occupied area
A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves
No full textWireless on-chip processing at millimeter waves still lacks key functions: quadrature generation enabling direct conversion architectures and simplifying phased-array systems, frequency division with an operating range wide enough to compensate
spreads due to component variations. This paper addresses the implementation of these functions, introducing new circuit solutions. The quadrature voltage-controlled oscillator (VCO) relies on a ring of two tuned VCOs, where the oscillation frequency depends on inter-stage passive components only, demonstrating low noise and accurate quadrature phases. Prototypes, realized in 65-nm CMOS, show 56–60.4-GHz tunable oscillation frequency, phase noise better than 95 dBc/Hz at 1-MHz offset in the tuning range, 1.5 maximum phase error while consuming 22 mA from a 1-V supply. The frequency divider is based on clocked differential amplifiers, working as dynamic CML latches, achieving high speed and low power simultaneously. A divider by 4 realized in 65-nm CMOS occupies 15 m 30 m, features an operating frequency programmable from 20 to 70 GHz in nine bands and consumes 6.5 mW
A mm-wave quadrature VCO based on magnetically coupled resonators
No full textSearch of a compact quadrature generator at around 60GHz with low phase noise at moderate power is the topic of this work. Discarding a double-frequency VCO followed by dividers-by-two given the high frequency range of operation, the most suitable topology borrowed by RF solutions is represented by cross-coupled LC voltage-controlled oscillators. However, the oscillation frequency dependence on the biasing current makes it susceptible to phase noise, close-in in particular. At mm-Waves, this is exacerbated by core devices of small dimensions to such an extent that 1/f noise remains dominant up to more than ~10MHz, making it unsuitable for stringent applications. On the contrary a ring of two VCOs magnetically coupled to each other has an oscillation frequency dependence on inter-stage passive components only, low 1/f noise together with good quadrature accuracy. The quadrature oscillator has been realized in a 65nm CMOS technology and prototypes show the following performances: 56-to-60.3GHz tunable oscillation frequency, phase noise better than -95dBc/Hz at 1MHz offset in the tuning range, 1.5° maximum phase error while consuming 22mA from a 1V supply
A 6.5mW Inductorless CMOS Frequency Divider by 4 Operating up to 70GHz
No full textDifferential amplifiers working as dynamic CML latches are proposed to realize compact, low power millimeter-waves frequency dividers. An inductorless divider by 4 realized in 65nm CMOS technology demonstrates an operating frequency programmable from 20GHz to 70GHz with a maximum power dissipation of 6.5mW from 1V supply
A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies
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