1,721,170 research outputs found
Soft errors in floating gate memory cells: A review
No full textSoft errors due to neutrons and alpha particles are among the main threats for the reliability of digital circuits operating at terrestrial level. These kinds of errors are typically associated with SRAMs and latches or DRAMs, and less frequently with non-volatile memories. In this paper we review the studies on the response of NAND and NOR Flash memories to ionizing particles, focusing on both single-level and multi-level cell architectures, manufactured in technologies down to a feature size of 25 nm. We discuss experimental error rates obtained with accelerated tests and identify the relative importance of neutron and alpha contributions. Technology scaling trends are finally discussed and modelled. © 2014 Elsevier Ltd. All rights reserved
Retention Errors in 65-nm Floating Gate Cells After Exposure to Heavy Ions
No full textThe retention of floating gate cells is studied up to one year after heavy-ion exposure, without using accelerated tests. Cross-sections of retention errors and threshold voltage shifts are discussed and compared with previous generation devices. The dependence of retention errors on the program level and irradiation angle is discussed and the underlying mechanisms are examined
Present and Future Non-volatile Memories for Space
No full textWe discuss non-volatile memories (NVM) for space applications. The focus will be both on technologies and devices aimed at the mainstream commercial markets and on rad-hard devices. Commercial NVMs are very attractive for space designers due to their large size (tens of Gbits), even though they have several issues related to ionizing radiation. Rad-hard NVMs offer radiation hardness, but are available only in small size (few Mbits). Most of the emphasis in this review paper will be on the current dominant technology in the mainstream market: floating gate flash memories. A comprehensive discussion of total dose and single event effects results for a wide cross section of NVMs will be presented. Finally, we will conclude with a cursory glance at other emerging non-volatile technologies
Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial FPGAs
No full textModeling MOSFET and circuit degradation through SPICE
No full textIn this work we investigate the impact of MOSFET degradation on the operation of real circuits through SPICE simulation. We show that by changing a few parameters in a LEVEL 3 model it is possible to reasonably account for the degradation in the characteristics of a single device following electrical stress. We then validate this approach on a simple circuit, a current mirror, and finally analyze the degradation of a more complex one, a voltage controlled oscillator
Alpha-induced soft errors in Floating Gate flash memories
No full textWe study the sensitivity to alpha particles of state-of-the-art Multi-Level Cell (MLC) and Single-Level Cell (SLC) NAND Floating Gate (FG) flash memories with NAND architecture. We show that starting from a feature size of 50 nm, MLC flash memories are sensitive to alpha particles, whereas SLC devices do not show any sensitivity down to a feature size of 34 nm. We calculate the alpha-induced soft error rates on the field, discuss technology trends in comparison to heavy-ions
Electrostatic discharge effects in ultrathin gate oxide MOSFETs
No full textThe effects of destructive and nondestructive electrostatic
discharge (ESD) events applied either to the gate or
drain terminal of MOSFETs with ultrathin gate oxide, emulating
the occurrence of an ESD event at the input or output IC pins,
respectively, were investigated. The authors studied how ESD may
affect MOSFET reliability in terms of time-to-breakdown (TTBD)
of the gate oxide and degradation of the transistor electrical characteristics
under subsequent electrical stresses. The main results
of this paper demonstrate that ESD stresses may modify the
MOSFET current driving capability immediately after stress and
during subsequent accelerated stresses but do not affect the TTBD
distributions. The damage introduced by ESD in MOSFETs increases
when the gate oxide thickness is reduced
Degradation of Static and Dynamic Behavior of CMOS Inverters during Constant and Pulsed Voltage Stress
No full textWe study the degradation of CMOS inverters under DC and pulsed stress conditions before the occurrence of the gate oxide breakdown. Our results show an overall speed reduction, caused by the transistor drain current drop, and a leftward shift of the inverter voltage transfer characteristics, due to a larger degradation of the PMOSFET as compared to the NMOSFET. We attribute this behavior to the build-up of defects/trapped charge featuring a different kinetics in P- and N-type MOSFETs
Degradation induced by X-ray Irradiation and Channel Hot Carrier Stresses in 130-nm NMOSFETs With Enclosed Layout
No full textWe present new experimental results about channel hot carrier degradation of enclosed layout transistors as a function of previous accumulated total ionizing dose, stress temperature, and transistor geometry. We show that the parametric degradation follows a power law, whose exponent is higher than in conventional open layout transistors, possibly due to a different diffusion geometry of hydrogen. Through physical simulation we attribute this effect to the electric field at the device corners, which leads to a non-uniform impact ionization. Previous irradiation reduces the channel hot carrier degradation in MOSFETs with 5.2-nm gate oxide, while having a minor influence with 2.2-nm gate dielectric
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