1,721,111 research outputs found
CMOS analog design for wireless communication
No full textThis paper presents an overview of new
problems arising from the ever and ever ubiquitous wireless communication systems. Low cost and high flexibility will be required for future generations of portable
termirials; for these reasons, the market share of CMOS technology is expected to grow quickly. Typical architectures of integrated portable transceivers are described, and solutions in CMOS technology are illustrated, outlining their advantages and drawbacks
Molecular dynamics simulation of the enterostatin APGPR and VPDPR peptides in water
No full textWe report on structural and dynamic properties in water of all the isomers of both peptides related to the trans and cis conformations of the peptide bonds preceding the proline (Pro) residues. Free-energy calculations indicate that the isomers having the Pro closer to the N-terminus (Pro1) in trans and the Pro2 in cis conformations are the most populated. Furthermore, the backbone is more flexible for APGPR than for VPDPR, and its conformation is more stable in the hydrophilic C-terminal moiety than in the hydrophobic N-terminal region
An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs
No full textThis paper presents an approach for simulation of mixed analog-digital CMOS integrated circuits, aiming at estimating crosstalk effects due to current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate is derived, and a representation of digital switching noise in time domain can be easily calculated through a dedicated computer program. This representation is used to perform an analog simulation using SPICE, to evaluate the propagation of the switching noise through the parasitic elements of the package and of the bonding wires. Simulation results for two case studies are presented
Simulation of crosstalk through bonding and package in mixed-signal CMOS ICs
No full textThis paper presents an approach for the simulation of mixed-signal CMOS integrated circuits, aiming at estimating crosstalk effects, by identifying possible sources of disturbances in analog-digital integrated systems, such as current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate can be derived. A computer program demonstrates the feasibility of the proposed approach, and a representation of digital switching noise in time domain has been derived. This representation has been used to perform an analog simulation using SPECTRE, to evaluate the propagation of the switching noise through the parasitic elements of the package and of the bonding wires
Simulation of mixed-signal circuits for crosstalk evaluation
No full textThis paper presents an approach for simulation of mixed-signal circuits, analyzing possible sources of disturbances in analog-digital integrated systems, such as current pulses drawn from voltage supplies. A closed-form expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate can be derived. A computer program demonstrates the feasibility of the proposed approach. Simulation results of a non-overlapped two-phase clock generator are presented
An analysis of current waveforms in CMOS logic cells for RF mixed circuits
No full textThis paper presents an approach for simulation of mixed-signal CMOS integrated circuits, aiming at estimating crosstalk effects, by identifying possible sources of disturbances in analog-digital integrated systems, such as current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate can be derived. A computer program demonstrates the feasibility of the proposed approach, and a representation of digital switching noise in frequency domain has been derived
Properties of digital switching currents in fully CMOS combinational logic
No full textIn this paper, we present a model to derive statistical properties of digital noise due to logic transitions of gates in a fully
CMOS combinational circuit. Switching activity of logic gates in a digital system is a deterministic process, depending on both circuit parameters and input signals. However, the huge number of logic blocks in a complex IC makes digital switching a cognitively stochastic process. For a combinational logic network, we can model
digital switching currents as stationary shot noise processes, deriving both their amplitude distributions and their power spectral densities. From the spectra of digital currents, we can also calculate
the spectral components and the rms value of disturbances injected into the on-chip power supply lines. The stochastic model for switching currents has been validated by comparing theoretical results with circuit simulations
Design considerations for analog blocks in mixed-signal CMOS ICs
No full textThis paper illustrates some design strategies for the design of mixed analog-digital integrated circuits in CMOS technology. In mixed-signal systems, crosstalk from switching logic gates can disturb the operation of analog circuitry. Therefore, it is necessary to take into account digital switching noise from early stages of design, by means of a suitable model. The analog designer should select the most suitable architectures with respect to crosstalk robustness. Finally, physical design must be optimized for the fabrication technology, to ensure a proper isolation between digital and analog sections
SOP restructuring by exploiting don’t cares
No full textIn this paper we define and study the properties of a generalized Shannon expansion on non-disjoint subsets of the Boolean space. This expansion consists in projecting the original function onto several overlapping subsets. Since the logic can be distributed among the projection subsets, input combinations asserted by a subset may be exploited as don’t cares for the other subsets. Our target is to exploit these don’t cares to obtain more compact networks based on SOP expressions. In particular, we show how to take advantage of don’t cares, derived from the projections, in two synthesis techniques, i.e., using a Boolean and an algebraic algorithm. Experimental results show that in the Boolean case 65% of the considered benchmarks achieve more compact area when implemented using projected don’t cares. The benefit in the algebraic approach is reduced (35% of instances benefit from the proposed technique), even though there are examples with an interesting decrease of the area
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