126 research outputs found
RRAM Crossbar-Based Fault-Tolerant Binary Neural Networks (BNNs)
No full textComputation-In Memory (CIM) using RRAM crossbar array is a promising solution to realize energy-efficient neuromorphic hardware, such as Binary Neural Networks (BNNs). However, RRAM faults restrict the applicability of CIM for BNN implementation. To address this issue, we propose a fault tolerance framework to mitigate the impact of RRAM faults on the accuracy of CIM-based BNN hardware. Evaluation results using MNIST, Fashion-MNIST and CIFAR-10 datasets demonstrate that the proposed framework outperforms the related works as it restores more than 99% of the RRAM fault induced accuracy reduction with relatively less overhead.Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer EngineeringQuantum & Computer Engineerin
Oxygen Isotopes in Authigenic Clay Minerals: Toward Building a Reliable Salinity Proxy
No full textMost clay minerals in sedimentary environments have traditionally been considered to be of detrital origin, but under certain conditions, authigenic clay minerals can form at low temperature through the transformation of precursor clays or as direct precipitates from lake water. Such clay minerals can hold important information about the prevailing climatic conditions during the time of deposition. We present the first quantitative reconstruction of salinity in paleolake Olduvai based on the oxygen‐isotope composition of authigenic clay minerals. We provide a framework illustrating that the isotopic signature of authigenic lacustrine clay minerals is related to the isotopic composition of paleo‐waters, and hence to paleosalinity. This new paleosalinity proxy shows that the early Pleistocene East African monsoon was driven by combinations of precession and obliquity forcing and subsequent changes in tropical sea surface temperatures. Such quantitative lacustrine paleosalinity estimates provide a new direction of research for modeling ecosystem change based on an ecologically relevant parameter.Originally published in:
Gebregiorgis, D., Deocampo, D. M., Longstaffe, F. J., Simpson, A., Ashley, G. M., Beverly, E. J., et al. (2020). Oxygen isotopes in authigenic clay minerals: Toward building a reliable salinity proxy. Geophysical Research Letters, 47, e2019GL085576. https://doi. org/10.1029/2019GL08557
Aging Mitigation Schemes for Embedded Memories
No full textWith the continuous miniaturization of CMOS technology into the nanometer regime, the reliability of SRAM memories is threatened by accelerated transistor aging such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) and gate oxide breakdown. Among these mechanisms BTI is known to be the primary aging mechanism in nanoscale devices. The overall effect of BTI is a gradual increase of threshold voltage (Vth). BTI significantly reduces the Static Noise Margin (SNM) of an SRAM cell and makes it more susceptible to failures. To address the impact of BTI in memory array a variety of bit flipping techniques has been proposed. However, all the proposed bit flipping techniques require at least an additional column to store the inversion flag which imposes considerably large area overhead. In this thesis, we propose two techniques to mitigate BTI induced aging in embedded memory: aging-aware instruction encoding and self-controlled bit flipping; both schemes take the workload into consideration. The aging-aware instruction encoding technique is based on changing the encoding of the Instruction Set Architecture (ISA) in order to balance the occurrence probabilities of 1s and 0s and therefore minimize the impact of BTI in the embedded memory. To evaluate this scheme, we used the Leon2 processor for course case study. A C++ based simulation environment was used to exhaustively search for an encoding resulting in a balanced occurrence probabilities of 0s and 1s. The simulation results revels that on average up to 30% SNM degradation improvement. Self-controlled bit flipping is based on inverting the content of the memory array during write operation with respect to a specific bit of the written word referred to as flip bit; this bit is left untouched during the write and used as a reference bit to indicate either the written data is inverted or not. Simulation results show that up to 33% SNM degradation improvement can be achieved. The area overhead of the proposed technique is the flip circuitry only. For this reason, our technique saves 64% of the area overhead induced by the periodic flipping techniques.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture
No full textEmerging memristor-based computing has the potential to achieve higher computational efficiency over conventional architectures. Bit-slicing scheme, which represents a single neural weight using multiple memristive devices, is usually introduced in memristor-based neural networks to meet high bit-precision demands. However, the accuracy of such networks can be significantly degraded due to non-zero minimum conductance of memristive devices. This paper proposes an unbalanced bit-slicing scheme; it uses smaller slice sizes for more important bits to provide higher sensing margin and reduces the impact of non-zero . Moreover, the unbalanced bit-slicing is assisted by 2’s complement arithmetic which further improves the accuracy. Simulation results show that our proposed scheme can achieve up to and accuracy compared to state-of-the-art for single-bit and two-bit configurations respectively, at reasonable energy overheads
Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs
No full textComputation-In-Memory (CIM) using memristor devices provides an energy-efficient hardware implementation of arithmetic and logic operations for numerous applications, such as neuromorphic computing and database query. However, memristor-based CIM suffers from various non-idealities such as conductance drift, read disturb, wire parasitics, endurance and device degradation. These negatively impact the computation accuracy of CIM. It is therefore essential to deal with these non-idealities and fabrication imperfections in order to harness the full potential of CIM. This paper discusses the non-ideality challenges and provides potential solutions. Furthermore, the paper outlines the potential future directions for CIM architectures.Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer EngineeringQuantum & Computer Engineerin
The implementation of an MBAN gateway
No full textEpilepsy is a severe neurological disorder that affects every aspect of a patient’s life. Unfortunately, there is no complete cure for everyone on the market yet. However, a lot of work has been done on seizure prevention. The entire project details the proof of concept implementation of a secure and reliable MBAN (Medical Body Area Network) used for seizure prevention. The principal objective of the MBAN system is to set up and maintain secure connections between the nodes of the MBAN system and store and analyze the received data in the cloud. Therefore, a suitable gateway is needed, which is created in this work. The gateway concerns a mobile application constructed with the Flutter SDK. The main ability of the applicaton is to communicate with the implantable medical device, which in the demonstration is the node the gateway is connected to using BLE. The application is designed for Android and iOS and is connected to the AWS cloud service in which the data is stored and analyzed with a simple function that checks whether the received heart rate is above a certain threshold. This function can be easily replaced by a more extensive function. In addition, the application displays user health metrics such as the heart rate, connection state, and it can update the firmware of the implantable medical device. The security measures taken in this project concern setting up the BLE connection with an OOB (Out Of Band) channel for key sharing, after which the key is used to encrypt the data streams. Additionally, the data in the cloud is encrypted
Mapping-aware Biased Training for Accurate Memristor-based Neural Networks
No full textMemristor-based computation-in-memory (CIM) can achieve high energy efficiency by processing the data within the memory, which makes it well-suited for applications like neural networks. However, memristors suffer from conductance variation problem where their programmed conductance values deviate from the desired values. Such variations lead to computational errors that result in degraded inference accuracy in CIM-based neural networks. In this paper, we present a mapping-aware biased training methodology to mitigate the impact of conductance variation on CIM-based neural networks. We first determine which conductance states of the memristor are inherently more immune to variation. The neural network is then trained under the constraint that important weights can only take numeric values which directly get mapped to such favorable states. Simulation results show that our proposed mapping-aware biased training achieves up to 2.4× hardware accuracy compared to the conventional training.Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer EngineeringQuantum & Computer Engineerin
Hierarchical Memory Diagnosis
No full textHigh-quality memory diagnosis methodologies are critical enablers for scaled memory devices as they reduce time to market and provide valuable information regarding test escapes and customer returns. This paper presents an efficient Hierarchical Memory Diagnosis (HMD) approach that accurately diagnoses faults in the entire memory. Faults are diagnosed hierarchically; first, their location, then their nature (i.e., static or dynamic), and finally, their functional fault model. The HMD approach leads to a more accurate diagnostic, enabling the precise identification of yield loss causes. Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Quantum & Computer EngineeringComputer Engineerin
Benchmarking and Algorithm Optimization for SENeCA: A RISC-V-based Neuromorphic Processor
No full textWith recent breakthroughs in AI (Artificial Intelligence) technology, the impact of AI on society can be felt in various fields. The market for AI software, for example, reached a valuation of \$62 billion in 2022. A growing number of new computer architectures specialized in running these AI software were also developed. At first they were run on conventional CPUs (Central Processing Unit) and GPUs (Graphical Processing Units), but then more specialized hardware emerged, such as the TPU (Tensor Processing Unit). However, since algorithms in these AI software are generally data-intensive, the power consumption became a problem. Therefore, as many of these algorithms were based on biological neural networks, there is a growing interest to develop hardware similarly based on principles found these networks as well to replicate their efficiency. This new architecture is known as neuromorphic architecture. However, a new architecture does not come without challenges. As a nascent and fragmented field, neuromorphic computing in general lacks a standardized benchmarking suite or methodology. In other, more mature fields, benchmarks are a standard way of evaluating the performance of different designs objectively and fairly. This thesis aims to propose and demonstrate a benchmarking methodology and implementation flow for neuromorphic processors. This methodology aims to measure the important performance metrics for a neuromorphic processor, both on the small scale of individual synaptic operations, and the large scale of performing an actual workload. The chosen workload is a keyword spotting program based on a simple DNN architecture, which detects a specific phrase in an audio recording. This workload was chosen due to its potential application in an environment where energy is limited, such as an embedded device.The neuromorphic processor that is the target of this benchmarking is SENeCA (short for Scalable Energy-efficient Neuromorphic Computer Architecture), a flexible and scalable design developed at IMEC The Netherlands. To implement the keyword spotting program on SENeCA, the keyword spotting program was rewritten and parsed. Since no physical chip implementation of SENeCA exists at the time of writing, the program was run on SENeCA using a HDL simulator. The execution time of the program is measured in detail, taking into account not only the total time, but also the time required to complete the specific stages of program. Afterwards, the power consumption of SENeCA during the execution of the program was measured using a power estimation software, both for the entire chip and its individual components. This is done both in average mode, obtaining the average power consumption over the total execution time, and in time-based mode, providing insight to the peak power and fluctuations over time. Then, the energy to solution is calculated using the execution time and power consumption. This process is done in multiple iterations, with a specific optimization done each iteration using SENeCA's accelerators. This provides insight into the impact of each optimization to power consumption and performance. Finally, a measurement of the energy consumption of SENeCA per individual synaptic operations is also done, allowing estimates of the energy consumption of future implementations.Electrical Engineering | Embedded System
Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM)
No full textSpiking Neural Networks (SNNs) can drastically improve the energy efficiency of neuromorphic computing through network sparsity and event-driven execution. Thus, SNNs have the potential to support practical cognitive tasks on resource constrained platforms, such as edge devices. To realize this, SNN requires energy-efficient hardware which can run applications with a limited energy budget. However, the conventional CMOS implementations cannot achieve this goal due to the various architectural and technological challenges. In this work, we address these issues by developing an energy-efficient and accurate SNN hardware based on Computation In-Memory (CIM) architecture using Resistive Random Access Memory (RRAM) devices. The developed SNN architecture is based on unsupervised Spike Time Dependent Plasticity (STDP) learning algorithm with online learning capability. Simulation results show that the proposed architecture is energy-efficient with a consumption of ≈20 fJ per spike, while maintaining state-of-the-art inference accuracy of 95% when evaluated using the MNIST dataset.Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer EngineeringQuantum & Computer Engineerin
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