1,720,972 research outputs found
Massively Parallel Nanoarchitectures: structures, algorithms and simulation tools
No full textThe exponential growth of computing power that we have been used-to since years is about to face new challenges, most notably for technical and economical reasons. It is highly debated when it will be time to go past traditional CMOS technology, but from ITRS data we know that traditional ultra-deep submicron devices are approaching fundamental physical limits. From an economical point of view, the extremely high costs of chip masks and production plants are posing substantial limitations to the development margins. The end of a remarkably successful era in computing is approaching then. It's the era where Moore's Law reigns and processing power per dollar doubles every year. A new era, though, is on the horizon [52]: the nanoelectronics era, with ever smaller devices and higher densities, to keep up with pace. Among the envisaged solutions to these arising problems, alternatives to traditional computation have been proposed, in the form of numerous so-called disruptive nanotechnologies. Some of the proposals innovate also the technological approach, moving from the conventional top-down process to a chemical self-assembly process. None of these effort is mature to the point to substitute CMOS any time soon, but this is the right time to be deeply involved in their study and contribute to their progress towards the moment when some of these will provide a valid alternative. The risk, else, would be to miss not just the next evolutionary step, but a revolution in the approach to computation. The fact that a clear winner is far and away from being declared among the competitors stresses the need to study different technology proposals. The scaling of the featured size of devices in disruptive nanotechnologies also requires to deal with added complexity, that is the price to pay for a great density advantage. Many nanotechnologies, and for sure the ones based on chemical self-assembly, suffer from two problems. First, the self-assembly nature of the process renders almost impossible to replicate complex aperiodic structures, as in the CMOS case. Then, the thermodynamical nature of the assembly makes structures sensitive to temperature variations. To put it more simply, disruptive nanotechnologies suffer from greater defect rates with respect to CMOS. Fault-tolerance techniques must be applied to fabrics, irrespective to the architecture of choice. The net gain, we said, on one side is the prospected density advantage, estimated in up to three orders of magnitude with respect to the limits traced by IRTS, plus a ultra-low power consumption: these are among the main reasons driving computational research in the field in this direction. This doctoral work focuses on the need to address specific questions that apply to many disruptive nanotechnologies. • Is it possible to cope with high defect rates? • How to interconnect nanoscale devices or logic blocks? • Which architectures are best fit for these high density devices? These questions are just an exemplification of the many questions that researchers are trying to answer. In our view, there is a methodological problem that has to be solved first and foremost. The problem is about which approach is scientifically sound to get data to answer the aforementioned question. It is our believe that building analytical models first, to study different technologies, would lead to conclusions that could hardly be considered convincing. In [27] we showed how an analytical model, despite its intricacy, is far from close to model the complexity of the system it mimics, and so are the attained results. From a methodological point of view, then, we argue that numerical simulations are needed to tackle the great complexity of these systems, irrespective of technology at hand, and this requires CAD tools specifically designed to study the nascent problems of emerging technology. Unfortunately, to the best of our knowledge, no such tool was developed before this work. Why, then, we observed a tendency to exploit existing tools to cross the bridge between nanotechnologies and nanoarchitectures? Was this due to the fact that existing tools were good at solving the new challenges as well? This could hardly be the reason why. In fact, it is rather difficult, if possible, to put up a toolchain of existing softwares, able to provide a complete workflow from nanodevice simulation to floorplanning, place and route, and nanoarchitecture simulation and evaluation, able to handle nanotechnology-related constraints. This work focuses on the development of such a tool, ToPoliNano. The software functionalities are described in details, alongside with attained results. It has the ability, starting from a circuit by parsing its VHDL description, to target different disruptive nanotechnologies (different Nanoarray-based architectures [143] and NanoMagneticLogics (NML), also known as Magnetic QCA (M-QCA) [76] supported at present time), to place and route it on a floorplan and then simulate it, in an integrated fashion. The tool has been used to study specific architectures devised to exploit the power of emerging technologies. ToPoliNano tool covers a broad range of abstraction levels, from the device level, to the circuit level, up to the architectural level. It is then possible to draw conclusions at architectural level starting from modeling at device level. This is critical to trust architectural results, usually prone to huge errors. Massively parallel architectures were studied to exploit regularity of these fabrics; this approach seems more promising than massive data parallelism. Logic and timing simulations have been performed, and results published in International Journals and Conferences [25, 26, 27, 32, 65, 77]. The organization of this document is as follows. Part I consists in Chapter 1, which is introductory to the technologies handled by ToPoliNano, providing background and state-of-the art information on the subject. Part II opens with Chapter 2, which is about general organization of the application, providing an overview of the specifications and of the most advanced characteristics of the ToPoliNano software. Chapter 3 provides information about the software at two levels of detail: introductory, if the subject is further developed in other parts of the work, informative else. Chapter 4 deals with details of the VHDL parsing module. Chapter 5 deals with details of the Input Stimuli Generator, while Chapter 6 thoroughly details implementation and results of the Simulation Engine(s) of the software. In Chapter 7 a key component for ToPoliNano's flexibility in dealing with different nanotechnologies is described: the Library Generator. Part II is closed by Chapter 8, in which a case study is presented, with an architecture proposal for biosequence analysis and simulation result
An Hardware Viewpoint on Biosequence Analysis: What's Next?
No full textBiosequence alignment recently received an increasing support from both commodity and dedicated hardware platforms. Processing capabilities are constantly rising, but still not satisfying the limitless requirements of this application. We give an insight on the contribution to this need that can possibly be expected from emerging technology devices and architectures, focusing as an example on nanofabrics based on silicon Nano Wires. By varying a few parameters we explore the solution space, and demonstrate with proper figures of merit how this family of beyond CMOS structures could be considered as the effective disruptive technology for biosequence analysis application
Nanoarray Architectures Multilevel Simulation
No full textDensity and regularity are deemed as the major advantages of nanoarray architectures based on nanowires. Literature demonstrated that proper reliability analyzes must be performed and solutions have to be devised to improve nanoarrays yield. Their complexity and high fault probability claim for specific design automation tools able to explore circuit solutions, performance and fault tolerant approaches. We envision a simulator conceived to carry on characterizations in terms of logic behavior, defect-induced output error rate assessment, switching activity, power and timing performance. Though already existing for traditional technology, a simulator based on specific technological and topological tiled nanoarray descriptions, and conceived to join both device and architecture levels, has never been attempted at the degree of accuracy we present. Our contribution is twofold. First, marking a difference with respect to the state of the art, we developed an algorithm based on an event-driven engine which works at switch level and is not simply built on top of cost functions evaluations. The straightforward advantage is the possibility to follow the evolution of dynamic control sequences throughout all the inner components of the nanoarray, and, as a consequence, to obtain circuit level characterization as a projection of the real internal parameters. Second, we added to our simulator the capability to inject faults with specific statistical distributions associated to the nanoarray topology. Here we extract output error rates and yield for one of the possible nanoarray structures proposed in literature, the NASIC. Results specificity and accuracy demonstrate the simulator trustworthiness, its effectiveness for extensive nanoarrays characterization and its suitability as a foundation for both higher architectural and lower device simulation levels. The aim of this work, then, is to provide insights into the intertwined relation between actual technology and circuit design for these emerging fabrics, and, as a consequence, to clarify how defects and variability affect circuits and systems performanc
Compact Model for Multiple Independent Gates Ambipolar Devices
Full text linkThe model presented is a charge-based model that assures the continuity of the current and the analytical derivability of charges to obtain the parasitic capacitances. It has been conceived to support the multiple independent gates, typical of nano-array structures, where each gate controls the charge in the channel. Charge conservation implies constant current in the different section of the multiple gate nanowire FET, making possible the development of a compact model for an arbitrary number of gates. The model has been used to describe different structures (i.e. number of gates, dimension of the single transistor and ranges of applied voltages) under static conditions and the results have been verified on Silvaco TCAD simulations. The modeling approach and the attained results for some cases of study will be presented and discusse
ToPoliNano: Nano-magnet Logic Circuits Design and Simulation
Full text linkAmong the emerging technologies Field-Coupled devices like Quantum dot Cellular Automata are particularly interesting. Of all the practical implementations of this principle NanoMagnet Logic shows many important features, such as a very low power consumption and the feasibility with up-to- date technology. However, its working principle, based on the interaction among neighbor cells, is quite different with respect to CMOS devices behavior. Dedicated design and simulation tools for this technology are necessary to further study this technology, but at the moment there are no such tools available in the scientific scenario. We present here ToPoliNano, a software developed as a design and simulation tool for NanoMagnet Logic, that can be easily adapted to many others emerging technologies, particularly to any kind of Field-Coupled devices. ToPoliNano allows to design circuits following a top-down approach similar to the one used in CMOS and to simulate them using a switch model specifically targeted for high complexity circuits. This tool greatly enhances the ability to analyze, explore and improve the design of Field- Coupled circuit
Testing Nanoarrays Fault Tolerance
Full text linkThe interesting expectations on nanoarray based
circuits are counterbalanced by critical issues related to reliability.
Nanowires and active devices currently cannot rely on a mature
technology and high rates of defects are still to be expected.
Our approach to evaluate the effects on nanoarray based circuits
behavior consists in simulating at switch level the precise behavior
of the circuit considering a statistical distribution of faults
throughout the tile area. We are able to reckon the output error
rate of nanoarray circuits as a function of defective rates and
defect distribution giving to both technologists and architects
directions to find possible solutions
ToPoliNano: A synthesis and simulation tool for NML circuits
No full textMany new emerging technologies are currently studied as possible substitute of CMOS transistors. Among these technologies one of the most interesting is the NanoMagnetic Logic (NML), which combines computation and memory in the same device. Although many works analyze this technology at the device level, an high level analysis on complex circuits is required to fully understand its potentialities. As an absolute novelty we present in this work a tool for automatic synthesis and simulation of NML circuits. Starting from a circuit described using VHDL language, the circuit physical layout is extracted, using all the technological constraints actually known. The circuit is then simulated using a behavioral model of the basic logic gates. This model is validated through micromagnetic low level simulations. Using ToPoliNano, which is highly modular and customizable, the possibility to explore and analyze realistic and complex NML circuits will be greatly improved
ToPoliNano: Nanoarchitectures Design Made Real
Full text linkMany facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or about which architecture is best fit for a specific application. Growing complexity requires taking into account many aspects of technology, application and architecture at the same time. Researchers face problems that are not new per se, but are now subject to very different constraints, that need to be captured by design tools. Among the emerging nanotechnologies, two-dimensional nanowire based arrays represent promising nanostructures, especially for massively parallel computing architectures. Few attempts have been done, aimed at giving the possibility to explore architectural solutions, deriving information from extensive and reliable nanoarray characterization. Moreover, in the nanotechnology arena there is still not a clear winner, so it is important to be able to target different technologies, not to miss the next big thing. We present a tool, ToPoliNano, that enables such a multi-technological characterization in terms of logic behavior, power and timing performance, area and layout constraints, on the basis of specific technological and topological descriptions. This tool can aid the design process, beside providing a comprehensive simulation framework for DC and timing simulations, and detailed power analysis. Design and simulation results will be shown for nanoarray-based circuits. ToPoliNano is the first real design tool that tackles the top down design of a circuit based on emerging technologie
Computationally Efficient Multiple-Independent-Gate Device Model
Full text linkNanowire field effect transistors (FETs) with multiple independent gates around a silicon channel feature ultimate gate control, and are regarded as promising candidates for next-generation transistors. Being inherently more complex than the conventional gate-all-around nanowire FETs, they require longer simulation time, especially with numerical simulations. We present a new model, enabling the efficient computation of voltages and current in modular semiconductor structures with an arbitrary number of independent gate regions. Its validity extends on gate-all-around MOSFETs, FinFETs, and gateless channels. It exploits existing models for conventional devices and builds results on top of these. Being completely general, the method is independent from the models used to describe each region, a charge-based model in our case. Applied to a multiindependent-gate nanowire FET structure, extensive comparison of the proposed method with results from physics-based TCAD Atlas software and with numerical exact results show very good agreement with relative errors of less than 1.8% for potentials and less than 4% for currents, under a broad variations of physical parameters as well as biasing conditions. Interpreted language implementation shows a performance advantage in excess of one order of magnitude with respect to standard optimized numerical methods, still providing excellent accuracy, and making it suitable for implementation in circuit simulators
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