1,720,970 research outputs found
Cost-effective 3D-IC design using near-field inter-tier wireless communication
No full textModern Internet of Things (IoT) devices are becoming increasingly complex, often incorporating a range of different components (sensors/processing/memory/logic) fabricated using a variety of process technologies. To integrate these disparate elements in a low-cost, small and power-efficient way, research has looked to ‘3D integration’ where several tiers are stacked and interconnected vertically within a single chip. Most research into 3D integration assumes the use of Through Silicon Vias (TSVs) to interconnect stacked tiers; however, TSVs are presently expensive to manufacture and only available in leading-edge process nodes, making them poorly suited to cost-sensitive IoT applications. In this thesis, wireless Inductive Coupling Links (ICLs) are investigated as an alternative to TSVs for vertical communication (and power delivery) within a 3D-IC. The motivation for focusing on wireless links is primarily cost-driven, as ICLs do not require 3D-specific fabrication processes and can facilitate simple pick-and-place assembly using only adhesive. Specifically, this work explores the design challenges associated with such ICLs, aiming to establish a standard interface that can be used for IoT-style 3D stacking applications. The key novel contributions include: (i) A low-energy ICL transceiver that uses timedomain encoding to reduce the number of transmit pulses, and hence overall energy, by over 13% when compared to existing solutions. (ii) A CAD tool for automated ICL inductor optimisation that significantly reduces the design time (by over 6 orders-of-magnitude) when compared with finite element tools, whilst maintaining an average accuracy within 7.8%. (iii) A near-field wireless clock link for many-tier clock synchronisation that achieves low-skew clock distribution across a wide range of frequencies (results show less than 61ps of clock skew across five tiers when operating between 50MHz and 2.3GHz). (iv) A hybrid ICL transceiver for concurrent wireless data and power transmission. The proposed transceiver can achieve wireless power transfer of up-to 2.0mW/link whilst simultaneously transferring 1.4Gbps of data using a BPSK scheme. These four contributions are also validated through two 3D-stacked silicon test-chip demonstrators, the first fabricated in 0.35 µm CMOS technology (showcasing the low-energy ICL transceiver), and the second fabricated in 65nm CMOS technology (showcasing wireless data, power and clock transmission as part of a 3D stacked Arm Cortex M0 SoC). Overall, this work represents an exciting step towards a new era in VLSI where IC designers can ‘pick-and-mix’ the functional circuit blocks and technologies within a given chip (in the form of separate semiconductor dies) and stack them together in a low-cost way using ICLs
Dataset supporting the paper entitled “A High-Speed Design Methodology for Inductive Coupling Links in 3D-ICs”
No full textThis dataset supports the article entitled 'A High-Speed Design Methodology for Inductive Coupling Links in 3D-ICs' accepted for publication in Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018</span
Dataset supporting the article entitled "CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs"
No full textThis dataset supports the article entitled "CoDAPT: A Concurrent Data And Power
Transceiver for Fully Wireless 3D-ICs" accepted for publication in IEEE Design Automation and Test in Europe.</span
A 3D-stacked cortex-M0 SoC with 20.3Gbps/mm2 7.1mW/mm2 simultaneous wireless inter-tier data and power transfer
No full textThis paper presents a 2-tier 3D-stacked Cortex-M0 SoC, in 65nm CMOS technology, with wireless inter-tier power and data transfer through an inductively coupled bus. The proposed design is the first implementation of a wireless link as part of a standard SoC bus, and achieves 20.3Gbps/mm2 data, and 7.1mW/mm2 power transfer simultaneously through a 250um channel. This also makes it the smallest ever reported inductive data and power link
A spike-latency transceiver with tuneable pulse control for low-energy wireless 3D integration
No full textWireless 3-D integration using inductive coupling links (ICLs) has recently gained attention as a low-cost alternative to through-silicon vias (TSVs) for interconnecting stacked silicon tiers. However, 3-D integration using ICLs is often criticized for its inferior energy efficiency compared with conventional approaches. To address this challenge, in this article, we present a low-energy ICL transceiver that combines a spike-latency encoding scheme (to reduce the number of energy-expensive analog transmit pulses by encoding data in the time domain) and a tunable current driver (to minimize the transmit energy depending on the given integration scenario). The proposed transceiver is modeled mathematically, simulated in 0.35- μ m, 65-nm, and 28-nm CMOS technologies and experimentally validated in a two-tier 3-D stacked silicon test chip. Silicon evaluation of the proposed modulation approach demonstrates an energy of 7.4 pJ/bit, representing a reduction >13% when compared with previously reported schemes (or 7.4% when also considering the additional energy overheads of peripheral clock timing control circuits). The simulated results show even greater energy savings (up to 28%) at more advanced technology nodes. Combined with the adaptive current driver, this results in a 7.7× improvement in energy per bit compared with the state-of-the-art implementations across the same communication distance, marking an important progression toward cost and energy-efficient 3-D integration.</p
Dataset supporting the article entitled "Design and Optimisation of Inductive Coupling Links for 3D-ICs"
No full textThis dataset supports the article entitled "Design and Optimisation of Inductive Coupling Links for 3D-ICs" accepted for publication in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.</span
Cost-effective 3D integration using inductive coupling links: Can we make stacking silicon as easy as stacking Lego?
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Dataset supporting the paper entitled “Power neutral performance scaling for energy harvesting MP-SoCs”
No full textThis dataset supports the paper entitled “Power Neutral Performance Scaling for Energy Harvesting MP-SoCs” accepted for publication</span
Dataset supporting the article entitled "A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration"
No full textThis dataset supports the article entitled: 'A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration', accepted for publication in the ACM/IEEE International Symposium on Low Power Electronics and Design , Lausanne, 2019.</span
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