9 research outputs found
Electrical Stability of MOS Structures With AlON and Al2O3 Dielectrics Deposited on n-and p-Type GaN
No full textThis article discusses the electrical stability of MOS structures on n-and p-type GaN for two different dielectrics, AlON and Al2O3, deposited by atomic layer deposition (ALD). Threshold voltage hysteresis was evaluated by means of capacitance-voltage (C-V ) double sweep measurements, performed on MOS capacitors. MOS structures on p-doped GaN show up to two orders of magnitude higher effective trapped charge density than on n-GaN. Moreover, AlON results in 10 times less trapped charge than Al 2 O 3 on p-GaN. The leakage current is also identified as an important factor in defining the electrical stability at high electric fields, due to the enhanced injection of electrons into the MOS stack. Electron trapping is shown to happen either at the dielectric-semiconductor interface or in border traps. AlON results in lower flat-band and threshold voltages likely due to the resulting fixed interface charge from surface reconstruction. The effect of the n-type doping density as well as of dry etch damage on the effective trapped charge after injection has been shown to be minimal. These results are important for different insulated gate device architectures. We show that extremely low threshold voltage hysteresis values can be reached in a trench-shaped gate GaN MOSFET using AlON as an interface dielectric
High-Temperature PBTI in Trench-Gate Vertical GaN Power MOSFETs: Role of Border and Semiconductor Traps
No full textFor the first time we investigate the positive threshold voltage instability in GaN-based trench gate MOSFETs in the high-temperature regime (150-240 degrees C). First, by inverse Laplace transform we determine the equivalent distribution of activation energies of the traps responsible for PBTI, with a peak at 0.75 eV from the conduction band of GaN. Second, we demonstrate that the recovery transients have a non-monotonic trend. This result, never described before, is attributed to the interplay between electron de-trapping from border traps, and hole de-trapping from defects in the p- type body layer, located 0.65 eV above the valence band energy of GaN, and preliminary ascribed to gallium vacancies in the semiconductor. Results provide relevant insight for optimizing the high-temperature stability of GaN vertical FETs
AlON gate dielectric and gate trench cleaning for improved relia-bility of vertical GaN MOSFET
No full textDevelopment and analysis of thick GaN drift layers on 200 mm CTE-matched substrate for vertical device processing
No full textAbstract This work reports the epitaxial growth of 8.5 µm-thick GaN layers on 200 mm engineered substrates with a polycrystalline AlN core (QST by QROMIS) for CMOS compatible processing of vertical GaN power devices. The epitaxial stack contains a 5 \upmu μ m thick drift layers with a Si doping density of 2 × 1016 cm−3 and total threading dislocation density of 4 × 108 cm−2. The thick drift layer requires fine-tuning of the epitaxial growth conditions to keep wafer bow under control and to avoid the formation of surface defects. Diode test structures processed with this epitaxial stack achieved hard breakdown voltages > 750 V, which is shown to be limited by impurity or metal diffusion from the contact metal stack into threading dislocations. Conductive Atomic Force Microscopy (cAFM) reveals some leakage contribution from mixed type dislocations, which have their core structure identified as the double 5/6 atom configuration by scanning transmission electron microscopy images. Modelling of the leakage conduction mechanism with one-dimensional hopping conduction shows good agreement with the experimental data, and the resulting fitting parameters are compared to similar findings on silicon substrates. The outcome of this work is important to understand the possibilities and limitations of vertical GaN devices fabricated on large diameter wafers
Output conductance at saturation like region on Line-TFET for different dimensions
No full textThis work presents the behavior of Line Tunneling Field Effect Transistors (Line-TFET) at the saturation like region with different device's dimensions. In spite of the drain current and transconductance (gm) of the Line-TFET being proportional to the gate área (LgxW, with Lg: length and W:width), the output conductance (gd) is shown to be independent on the gate length at deep saturation. This unique behavior was observed experimentally and explained by numerical simulations. The conduction mechanisms are discussed and parasitic source to drain tunneling is found to be the main responsible for the output conductance value at the deep saturation like region, which doesn't depend upon Lg. Its impact on analog circuit design is also addressed, revealing fundamental differences of analog design using Line-TFET devices and MOSFET. It is revealed that if the designer wishes to increase the circuit voltage gain, this can be done by increasing the transconductance or the output resistance with Line-TFETs, as for MOSFETs only the latter option is available.LSI/PSI/USP University of Sao PauloUNESP Sao Paulo State UniversityUNESP Sao Paulo State Universit
Output conductance at saturation like region on Line-TFET for different dimensions
No full textThis work presents the behavior of Line Tunneling Field Effect Transistors (Line-TFET) at the saturation like region with different device's dimensions. In spite of the drain current and transconductance (gm) of the Line-TFET being proportional to the gate area (LgxW, with Lg: length and W:width), the output conductance (gd) is shown to be independent on the gate length at deep saturation. This unique behavior was observed experimentally and explained by numerical simulations. The conduction mechanisms are discussed and parasitic source to drain tunneling is found to be the main responsible for the output conductance value at the deep saturation like region, which doesn't depend upon Lg. Its impact on analog circuit design is also addressed, revealing fundamental differences of analog design using Line-TFET devices and MOSFET. It is revealed that if the designer wishes to increase the circuit voltage gain, this can be done by increasing the transconductance or the output resistance with Line-TFETs, as for MOSFETs only the latter option is available.Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Univ Sao Paulo, LSI PSI USP, Sao Paulo, BrazilSao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, BrazilSao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, Brazi
Two-stage amplifier design based on experimental Line-Tunnel FET data
No full textThis work presents for the first time a two-stage operational transconductance amplifier (OTA) design based on experimental Line-TFET devices. To account for different parasitic effects, make the project more feasible and avoid complicated and inaccurate analytical modelling, experimental devices are measured and the data is used in lookup tables to be coded in Verilog-A hardware description language. A two-stage amplifier is designed considering the particularities of these devices and the figures of merit achieved are related to its characteristics, including the non-idealities verified in the experimental characterization. The designed amplifier exhibits extremely high open loop voltage gain, good performance and bandwidth when compared with other TFET designs, at moderate power supply voltage with high output swing and low power consumption. The results obtained are compared with MOSFET designs and with other TFET based amplifiers found in the literature.LSI/PSI/USP University of Sao PauloUnesp Sao Paulo State UniversityImecClaRooE.E. Dept Ku LeuvenUnesp Sao Paulo State Universit
