130,978 research outputs found
Petrus Hispanus O.P. Auctor Summularum (III) ¿”Petrus Alfonsi” o “Petrus Ferrandi”?
No full textThis article aims to be a complement and continuation of my earlier work on the figure of Petrus Hispanus O. P., Auctor Summularum. First I bring to light some new documents in connection with the issues already examined in my 1997 and 2001 articles. Next, I deal with the questions postponed in my 2001 article: the problems concerning the figure of “Petrus Ferrandi” and his possible connection with the “auctor Summularum”, as well as Tugwell’s arguments against the hypothesis of the possible identity of the two figures, now examined from the perspective of the author of the Legenda prima. After analysing evidences from very diverse origin, I affirm, on the one hand, that the hypothesis of the identity of “Petrus Ferrandi” and “Petrus Hispanus” might be correct and, on the other hand, that there are no conclusive arguments that force us to affirm with certainty that the author of the Legenda prima is Pedro Ferrando. Although the analyses do not allow yet to determine whether the “auctor Summularum” is “Petrus Alfonsi” or “Petrus Ferrandi”, the evidence gathered and the connections set up will no doubt contribute to guide future research around the figure of “Petrus Hispanus”.Este artículo pretende ser complemento y continuación de mis anteriores trabajos sobre la figura de Petrus Hispanus O. P., Auctor Summularum. Comienzo presentando algunos nuevos documentos relacionados con las cuestiones ya examinadas en mis artículos de 1997 y 2001. A continuación, me ocupo de las cuestiones aplazadas en el artículo de 2001: los problemas relativos a la figura de “Petrus Ferrandi” y su posible relación con el “auctor Summularum”, así como los argumentos de Tugwell contra la hipótesis de la posible identidad de estas dos figuras, examinados ahora desde la perspectiva del autor de la Legenda prima. Tras analizar testimonios procedentes de muy diversos ámbitos, afirmo, por una parte, que la hipótesis de la identidad entre “Petrus Ferrandi” y “Petrus Hispanus” podría ser correcta y, por otra parte, que no hay argumentos concluyentes que obliguen a afirmar con seguridad que el autor de la Legenda prima es Pedro Ferrando. Aunque los análisis no permiten por el momento determinar si es “Petrus Alfonsi” o “Petrus Ferrandi” el “auctor Summularum”, los testimonios recogidos y las conexiones establecidas contribuirán, sin duda, a orientar futuras investigaciones en torno a la figura de “Petrus Hispanus”
Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques
No full textThis pap er presents a novel optimization algorithm for FSM networks that relies on sequential test generation and redun- dancy removal. The implementation of the prop osed approach, which is based on the exploitation of input don't care sequences through regular language intersection, is fully symb olic. Exp er- imental results, obtained on a large set of standard b enchmarks, improve over the ones of state-of-the-art metho d
How an ''evolving'' fault model improves the behavioral test generation
No full textBy considering test costs at behavioral level, test problems can be pointed out during the first phases of the design flow. Thus, in case either some testability problems are identified or the size (and hence the cost) of the test set results to be too high, the designer or the high level synthesis tool can modify the circuit to reduce such testability problems. The main problem is the correspondence between the behavioral and RT or gate level fault models. To overcome such limitation, the paper presents a design flow based on the behavioral fault model modification (''evolution'') depending on the actual RTL implementation
Behavioral Test Generation for Test Embedding
No full textBehavioral Test Generation for Test Embeddin
Behavioral test generation for the selection of BIST logic
No full textThe identification of the most suited BIST architecture is one of the bottlenecks in the actual application of self-testing techniques. The aim of this paper is the investigation of possible relations between the behavioral level specification of the circuit, and the structural level, where BIST logic is inserted. We propose to use behavioral test patterns to guide the selection of the most appropriate BIST architecture with respect to the given application as a trade-off between fault coverage and area overhead. The correlation between the behavioral analysis and the actual fault coverage of the inserted BIST logic has been shown on a number of benchmarks
Implicit test generation for behavioral VHDL models
No full textThis paper proposes a behavioral-level test pattern generation algorithm for behavioral VHDL descriptions. The proposed approach is based on the comparison between the implicit description of the fault-free behavior and the faulty behavior, obtained through a new behavioral fault model. The paper will experimentally show that the test patterns generated at the behavioral level provide a very high stuck-at fault coverage when applied to different gate-level implementations of the given VHDL behavioral specification. Gate-level ATPGs applied on these same circuits obtain lower fault coverage, in particular when considering circuits with hard to detect fault
Testability Alternatives Exploration through Functional Testing
No full textThe aim of this paper is to show the effectiveness of a high-level approach to testability analysis and test pattern generation, when analyzing different classes of architectures implementing the same specification. A unique test set is derived on the behavioral specification, based on a functional error model, which shows a high correlation with the single stuck-at-gate-level fault model. Such a test set is then tailored to the particular gate-level implementation by transforming it into a specific test sequence, based on the scheduling adopted by the high-level synthesis. Experimental results show that the application of such test sequences allows one to accurately evaluate the testability of the architecture in terms of gate-level fault coverage, in a fraction of the time required by a gate-level test pattern generato
Power Estimation of Behavioral Descriptions
No full textThis paper presents a methodology for power estimation of designs described at the Behavioral-level as the interconnection of functional modules. The input/output Behavior of each module is implicitly stored using BDDs, and the power consumed By the network is estimated using a novel and accurate entropy-based approach. As a demonstration example, we have used the proposed power estimation technique to evaluate and compare the effects of some architectural transformations applied to a reference design specification on the power dissipation of the corresponding implementations
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells
No full textNowadays, design issues related to physical design and scalability are becoming the main bottlenecks of modern tools for technology mapping, limiting the usage of large cells. On the other hand, the generation of regular macro cells, such as compound gates, are becoming interesting from the manufacturing point of view, but they need to be properly integrated into the existing industrial design flows. In this paper, we present an efficient methodology for identifying the cells that can extend an existing standard-cell library. We validated our approach on different benchmarks targeting area minimization and we also analyzed timing, power consumption and routing effects for the final circuit implementation
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