1,721,162 research outputs found
Reduction of fault detection costs through a BDD formalism
No full textThe paper presents a methodology for an efficient testability analysis of complex VLSI circuit. It is based on controllability/observability evaluation using Binary Decision Diagrams (BDD). Efficiency is improved by intelligent use of intermediate results. © 1994
Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications
Full text linkField Programmable Gate Arrays (FPGAs) are becoming an appealing technology in datacenters and High Performance Computing. High-Level Synthesis (HLS) of multi-threaded parallel programs is increasingly used to extract parallelism. Despite great leaps forward in HLS and related debugging methodologies, there is a lack of contributions in automated bug identification for HLS of multi-threaded programs. This work defines a methodology to automatically detect and isolate bugs in parallel circuits generated with HLS. The technique relies on hardware/software Discrepancy Analysis and exploits a pattern-matching algorithm based on Finite State Automata to compare multiple hardware and software threads. Overhead, advantages, and limitations are evaluated on designs generated with an open-source HLS compiler supporting OpenMP
Synthesis of complex control structures from behavioral SystemC models
No full textIn this paper, we present the results of a set of experiments we conducted in order to evaluate the viability of behavioral synthesis, relying on the tools available at the moment in the EDA market. To accomplish this we modelled a complex PCI bus interface in SystemC using a behavioral style of description. Then we tried to synthesize it by means of the Synopsis CoCentric SystemC compiler tool. The problems arisen during synthesis, in particular those concerned with the cycle-accurate timing behavior of the synthesized circuit, were addressed. After analyzing them, possible solutions were proposed, where possible. Finally, a summary of the pros and cons of the behavioral synthesis in SystemC is presented
Tensor Optimization for High-Level Synthesis Design Flows
Full text linkImproving data locality of tensor data structures is a crucial optimization for maximizing the performance of Machine Learning and intensive Linear Algebra applications. While CPUs and GPUs improve data locality by means of automated caching mechanisms, FPGAs let the developer specify data structure allocation. Although this feature enables a high degree of customizability, the increasing complexity and memory footprint of modern applications prevent considering any manual approach to find an optimal allocation. For this reason, we propose a compiler optimization to automatically improve the tensor allocation of high-level software descriptions. The optimization is controlled by a flexible cost model that can be tuned by means of simple yet expressive callback functions. In this way, the user can tailor the optimization strategy with respect to the optimization goal. We tested our methodology integrating our optimization in the Bambu open-source HLS framework. In this setting, we achieved a 14% speedup on the digit recognition version proposed by the Rosetta benchmark. Moreover, we tested our optimization on the CHStone benchmark suite, achieving an average of 6% speedup. Finally, we applied our methodology on two industrial examples from the aerospace domain obtaining a 15% speedup. As a final step, we tested the versatility of our methodology inserting our optimization in the Clang software optimization flow achieving a 12% speedup on the Rosetta benchmark when running on CPU
Abstract: Speeding-Up Memory Intensive Applications through Adaptive Hardware Accelerators
No full textData-path testability analysis based on BDDs
No full textOptimal application of Design for Testability techniques extends on an efficient testability analysis. Circuit complexity does not allow traditional testability analysis approach to perform efficiently. Therefore an higher abstraction level must be considered. This paper presents a methodology for controllability and observability verification at a functional level, starting from a VHDL description of the system architecture. Since efficiency is a primary goal for industrial application of such technique, a representation based on Binary Decision Diagrams has been introduced and its effectiveness is presented on telecom application
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