1,721,116 research outputs found
Pulse propagation for the detection of small delay defects
No full textThis paper addresses the problems related to resistive opens and bridging faults which cannot be detected using delay fault testing because they lie out of the most critical paths. Even if the induced defect is not large enough to result in timing violations, these faults may give rise to reliability problems. To detect them, we propose a testing method that is based on the propagation of pulses within the faulty circuit and that exploits the degraded capabity of faulty paths to propagate pulses. The effectiveness of the proposed method is analyzed at the electrical level and compared with the use of reduced clock period which can detect the same class of faults. Results show similar performance in the case of resistive opens and better performance in the case of bridgings. Moreover, the proposed approach is not affected by problems on the clock distribution network. © 2007 EDAA
Problems due to open faults in the interconnections of self-checking data-paths
No full textIn this work, the problem of open faults affecting the interconnections of SC circuits composed by data-path and control is analyzed. In particular it is shown that, in case opens affect control signals, some problems may arise even if both control and data-path signals are concurrently checked. In particular, wrong codewords may be generated at the outputs of multiplexers and registers. To address this problem, new registers and multiplexers are proposed which allow the design data-paths which are TSC with respect to opens (and resistive opens). These components are also TSC with respect to stuck-at, transistor and gross delay faults. They present a good testability with respect to resistive bridgings. © 2002 IEEE
High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations
No full textThe growing dispersion of parameters in CMOS ICs poses relevant uncertainties on gate output
conductances and logic thresholds that affect bridging fault (BF) detection. To analyze the quality
of fault simulation and test generation tools using nominal IC parameters, we studied BF detection
as a function of the standard deviation of parameters: results show that a single test vector cannot
ensure acceptable escape probabilities. Conversely, the minimal number of test vectors providing
null escape probability is upper-bounded with respect to variations of parameters, as verified by
Monte Carlo electrical-level simulations. We propose a method to derive such minimal test sets for
low frequency testing. A fault simulator and a test generator have been developed supporting the
search of minimal test sets targeting a null escape probability
Delineation of syn-eruptive floods in the circumvesuvian plain (southern Italy)
No full textDuring explosive eruptions the deposition of
fine-grained volcanic ash fallout reduces soil permeability,
favouring runoff of meteoric water and thus increasing the
occurrence of catastrophic floods. A fully dynamic, twodimensional
model was used to simulate flooding scenarios
in the Vesuvian area following an explosive volcanic eruption.
The highest risk occurs in the catchment area of the
Acerra-Nola Plain N and NE of Vesuvius. This plain has a
population of 70,000 living in low-lying areas. This catchment
area is vulnerable to ash fall because it lies downwind
of the dominant synoptic circulation and it lacks a natural
outflow toward the sea. Our numerical simulations predict
dangerous scenarios, even in quiescent periods, during extreme
rain events (return periods of 200 years have been
considered), and a significant increase in the extent of the flooded areas due to renewed volcanic activity. Based on these simulations a hazard zonation has been proposed
A Probabilistic Fault Model for “Analog” Faults in Digital CMOS Circuits
No full textThis paper presents a probabilistic approach to the detection of analog faults (i.e., transistors stuck-on and bridgings) in CMOS circuits that depends on the conductances of faulty and fault-free networks. It is shown that unrealistic fault coverages can be obtained by simply assigning constant values to the conductances of transistors and bridgings and by comparing the resultant conductances of faulty and fault-free conflicting networks. To solve this problem, in this paper all conductances are considered as random variables with normal distribution. Conductance distributions of complex conflicting networks can be easily evaluated and the detection probability of each fault is determined. The expected coverage of analog faults is known at the end of a fault simulation. This result is shown to be more realistic than those obtained in a deterministic way. Fault coverages of analog faults obtained by means of a gate-level fault simulator are discussed for a complex FCMOS benchmark. © 1992, IEE
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