1,721,131 research outputs found
Configurable network-on-chip router macrocells
Full text linkThis paper presents a configurable architecture for Network-on-Chip (NoC) router macrocells, and a methodology to streamline their design and configuration. The methodology addresses the typical problems experienced by design and verification engineers when coding highly configurable intellectual property macrocells at Register Transfer Level (RTL) with hundreds of parameters and thousands of resulting configurations. A NoC infrastructure for a Multi Processor System-on-Chip (MPSoC) may require tens or hundreds of router macrocells. Therefore, managing the configuration design space is becoming a bottleneck for the design and verification of many-core processing systems. The proposed generation flow is illustrated on a real-world NoC router core. Its configurable architecture is compliant with several NoC topologies such as Ring, Octagon, Spidergon and 2D mesh typically used in many-core processing platforms. The generation flow allows for a reduction in the database code size, up to 70% in our experiments, and a contraction of three orders of magnitudes of the verification space vs. conventional design flows of RTL macrocells. The validity of the approach is also confirmed by synthesizing the generated router macrocells in nanoscale CMOS technology. The achieved performance compare well to the state-of-the-art in terms of low latency and low circuit complexit
Design and Preliminary Validation of an Assisted Driving System for Obstacle Avoidance Based on Reinforcement Learning Applied to Electrified Wheelchairs
No full textOperating a motorized wheelchair poses inherent risks and demands substantial cognitive effort to achieve effective environmental awareness. Consequently, individuals with severe disabilities face heightened risk, leading to diminished social engagement which impacts their overall well-being. Therefore, we have developed a collaborative driving system for obstacle avoidance based on a trained reinforcement learning (RL) algorithm. The system interfaces with the user through a joystick, capturing the desired direction and speed, while a lidar positioned in front of the wheelchair provides information about obstacle distribution. Taking both inputs into account, the system generates a pair of forward and rotational speeds that prioritize obstacle avoidance while closely aligning with the user’s commands. Preliminary validation through simulations involved comparing the RL algorithm with the absence of an assistive system. The results are promising, showcasing that the RL algorithm reduces collisions without imposing constraints on the desired speed. Ongoing research is dedicated to expanding tests and conducting comparisons with traditional obstacle avoidance algorithms
A configurable hardware word re-ordering block for multi-lane communication protocols: Design and use case
Full text linkData rate requirements, from consumer application to automotive and aerospace grew rapidly in the last years. This led to the development of a series of communication protocols (i.e. Ethernet, PCI-Express, RapidIO and SpaceFibre), which use more than one communication lane, both to speed up data rate and to increase link reliability. Some of these protocols, such as SpaceFibre, are able to detect real-time changes in the number of active lanes and to adapt the data flow appropriately, providing a flexible solution, robust to lane failures. This results in a real time varying data path in the lower layers of the data handling system. The aim of this paper is to propose the architecture of a hardware block capable of reading a fixed number of words from a host FIFO and shaping them on a real time variable number of words equal to the number of active lanes
On the frequency carrier offset and symbol timing estimation for ccsds 131.2-b-1 high data-rate telemetry receivers
Full text linkIn recent years there have been significant developments in satellite transmitter technology to follow the rapid innovation of sensors on-board new satellites. The CCSDS 131.2-B-1 standard for telemetry downlink, released in 2012, is part of the next generation of standards that aims to support the increased data-rate caused by these improvements in resolution. As a result of its relative novelty, this standard currently lacks in-depth analysis by researchers, but it is also strongly supported by the European Space Agency (ESA) for future missions. For these reasons, it seems important to evaluate how major receiver sub-components, such as timing recovery and carrier frequency correction, can be designed and implemented in new receivers that support this standard. The timing error detectors (TED) and frequency error detectors (FED) were therefore studied on the specific peculiarities of CCSDS 131.2-B-1 in its usual environment of Low Earth Orbit (LEO). Estimators have been evaluated highlighting performances, trade-offs and peculiarities of each one with respect to corresponding architectural choices. Finally, a receiver architecture derived from the paper considerations is proposed in the aim of supporting very different mission scenarios. Specifically, the realized architecture employs a parallel feedforward estimator for the timing recovery section and a novel multi-algorithm feedback frequency correction loop to efficiently cover both low symbol rates (5 Mbaud) and high data-rates (up to 500 Mbaud). This solution represents a good trade-off to support these scenarios in a very compact footprint by pushing the clock frequency to the FPGA limit. The FPGA resources occupation on a Zynq Ultrascale+ RFSoC XCZU28DR FPGA is 5202 LUT, 4851 FF, 5 BRAM, and 21 DSP for the timing recovery part, while the frequency recovery section occupies 1723 LUT, 1511 FF, 2.5 BRAM and 32 DSP
VHDL design of a spacefibre routing switch
Full text linkThe technology advancement of satellite instruments requires increasingly fast interconnection technologies, for which no stan-dardised solution exists. SpaceFibre is the forthcoming protocol promising to overcome the limitation of its predecessor SpaceWire, offering data-rate higher than 1 Gbps. However, while several implementations of the SpaceFibre IP already exist, its Network Layer is still at experimental level. This article describes the architecture of an implemented SpaceFibre Routing Switch and provides synthesis results for common FPGAs
A YOLOv2 convolutional neural network-based Human-Machine Interface for the control of assistive robotic manipulators
Full text linkDuring the last years, the mobility of people with upper limb disabilities and constrained on power wheelchairs is empowered by robotic arms. Nowadays, even though modern manipulators offer a high number of functionalities, some users cannot exploit all those potentialities due to their reduced manual skills, even if capable of driving the wheelchair by means of proper Human-Machine Interface (HMI). Owing to that, this work proposes a low-cost manipulator realizing only simple tasks and controllable by three different graphical HMI. The latter are empowered using a You Only Look Once (YOLO) v2 Convolutional Neural Network that analyzes the video stream generated by a camera placed on the robotic arm end-effector and recognizes the objects with which the user can interact. Such objects are shown to the user in the HMI surrounded by a bounding box. When the user selects one of the recognized objects, the target position information is exploited by an automatic close-feedback algorithm which leads the manipulator to automatically perform the desired task. A test procedure showed that the accuracy in reaching the desired target is 78%. The produced HMIs were appreciated by different user categories, obtaining a mean score of 8.13/10
FPGA Implementation of a Configurable Vocal Feature Extraction Embedded System for Dysarthric Speech Recognition
No full textIn the last few years, users have been increasingly demanding for a hands-free interaction with their digital devices. This kind of technology is even more useful if used by people with disabilities, improving their quality of life. In particular, speech-impaired users (e.g. dysarthric speakers) represent a big challenge for an Automatic Speech Recognition (ASR) system because standard approaches are ineffective with them. Therefore, new speech analysis algorithms are implemented and generally tested on off-line datasets, but their performance can differ from a real case. Hence comes the need to easily validate their performance in a real scenario. The work presented in this paper shows an implementation of a highly configurable off-line embedded system for both MFCC and Mel Filterbanks extraction equipped with an on-board microphone. The results show that our system performs well in a real scenario case in terms of both power consumption and word error rate
A representative SpaceFibre network evaluation: Features, performances and future trends
No full textSpaceFibre is a high-speed satellite on-board communication protocol. It allows high data rates (up to 6.25 Gbps per lane), advanced quality of service, fault detection isolation and recovery. Different SpaceFibre nodes can be combined, together with a SpaceFibre routing switch, to form a network. This work aims to describe the set-up of a SpaceFibre network, made of independently developed nodes. The performance of a simplified version of the network is then evaluated and measured, in terms of jitter and latency, for both data packets and broadcast messages, providing a first literature contribution about innovative SpaceFibre network timing performances. It will be a useful indication for future system adopters and could be the baseline for future in-depth measurement and investigation
Exploring GPS L1 C/A Fast Acquisition with COTS FPGA
No full textIn this work we create an environment to validate and implement a GPS L1 C/A fast acquisition core on COTS FPGAs. The frequency domain PCPS algorithm is studied on a Scilab test bench and the results are compared with the outputs of the GNSS-SDR simulator. Then all the PCPS algorithmic blocks are designed and fitted on an FPGA. The hardware core is successfully used to acquire GPS L1 C/A signal records. Timing and area results are analyzed to understand how to extend the design to modern GPS signals
Automatic Generation of 3D Printable Tactile Paintings for the Visually Impaired
No full textTraditional 3D scanning techniques can be used effectively to replicate solid objects such as statues, to produce low-cost replicas allowed to be touched by visitors. However, such techniques require expensive equipment and precise 3D scanning, also they are unsuitable for rendering 2D paintings as 3D models. In order to address these limitations, we developed a scalable, low-cost solution to produce braille-like readable 3D models of 2D paintings. We directly addressed the problem of rendering the shades of color and brushstrokes styles present in the original painting as an embossed composable surface. We repurposed a technique first used in 1634 by the Italian heraldist Padre Silvestro da Pietrasanta to reproduce the colors of coat of arms with only lines and dots. We acknowledge its simplicity and effectiveness in conveying color information and its feasibility for modern 3D printing. As an extension to the basic color conversion, we included smooth color transition and textural content. With this work we aim at including more people with visual disabilities in experiencing our vast cultural heritage
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