29 research outputs found
Modeling and analysis of TSV noise coupling and suppression methods for 20nm node and beyond
No full textWith the technology nodes keep advancing, the application of TSV(Through Silicon Via) technology in 3D integration is faced with more challenges. The shift from via-last to via-middle fabrication scheme, the ever-increasing density of TSV, the reduction in supply voltage and the increase in frequency of on-chip local clock, all pose threat to signal/power integrity of the TSV system. In this paper, the noise coupling effect between TSVs and corresponding suppression methods were modeled and analyzed. Effect of variations of structural parameters on noise coupling are investigated and results are explained based on specifications of advanced technology node. In order to alleviate noise effect under fine pitch scenario, different noise suppression methods are discussed and compared. The guard-ring didn't demonstrate much noise reduction over the whole frequency spectrum, with slightly better performance within the low frequency range. The buried oxide layer of SOI technology also showed little suppression effect in blocking substrate noise. However, the TSV array scheme is significantly effective in noise suppression over the whole frequency spectrum. ? 2014 IEEE.EI
Simulation-based Investigation in Effects of Design Parameters on Electrical Characters for a TSV-bump Combination
No full textThe silicon industry has witnessed a half-century gallop of electronics. When technologies reached their limits, new technologies are budding out and prolong the unbreakable Moore's Law. This time, Through Silicon Via (TSV) is considered the most promising technology trend in the next decade. In this paper, we study the electrical characters of a TSV-bump combination under the ground-signal-ground configuration. Effects of design parameters, including geometries and material parameters, on systematic electrical characteristics are investigated and concluded in terms of scatter (S) parameters by a 3D electromagnetic solver. To verify the simulated electrical performance, this paper proposes the equivalent electrical model of the GSG configuration consisting of RLCG parasitic elements. Analytical models are assigned to each parasitic component by employing classical equivalent circuit models of different types of transmission lines. Good agreement is achieved on S-parameters between the 3D electromagnetic solver and the proposed lumped circuit model in the frequency range of 0.1-20GHz.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000319836000028&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701Engineering, Electrical & ElectronicEICPCI-S(ISTP)
Stabilization and Utilization of Coupling MOS Capacitance between TSVs
No full textThrough-silicon via (TSV) is a key enabler for future 3-D integrated circuits. Due to MOS (Metal-Oxide-Semiconductor) effect, the coupling capacitor between TSVs is actually a varactor under different signal/power voltages. This paper offers a discussion on the stabilization and utilization of the TSV varactor for different systems. For digital systems, it is important to ensure that TSV capacitance is stable within the operating voltage. Therefore, different methods are proposed and compared to stabilize the TSV coupling capacitance. For reconfigurable systems, the possibility of the TSV varactor serving as the tunable capacitor is demonstrated by designing a voltage controlled tunable low-pass filter with a TSV pair. The doping profile of the substrate is modified to maintain a reasonable quality factor of the TSV varactor. The simulated results show that the filter has a cutoff frequency shifting from 1.85GHz at 0V to 2.23GHz at 1V, resulting in a tuning range of +/- 9% centered at 2.04GHz.National Basic Research Program of China [2015CB0572]; Importation and Development of High-Caliber Talents Project of Beijing Municipal Institutions [CITTCD20150320]; National Natural Science Foundation of China [61176102]; National Center for Advanced Packaging, ChinaCPCI-S(ISTP)347-35
Bias-dependent High Frequency Characterization of Through-Silicon Via (TSV) for 3D Integration
No full textIn this paper, high frequency measurement of TSV structures under different DC bias conditions are carried out. The impact of the MOS capacitance effect of TSV on its transmission performance is analyzed. Capacitance and conductance parameters of TSV are extracted and compared with numerical calculations.CPCI-S(ISTP)[email protected]; [email protected]
Characteristics of Coupling Capacitance Between Signal-Ground TSVs Considering MOS Effect in Silicon Interposers
No full textAlong with extensive applications of through-silicon vias (TSVs) in 3-D systems, such as digital, logic, and memory modules, the accurate modeling of coupling capacitance between the TSVs is becoming indispensable to the signal integrity analysis of the system design. In this paper, the static characteristics of potential, electric field, and charges between signal-ground TSVs in a floating substrate are investigated, and accordingly, the effect of MOS capacitance on the coupling capacitance between signal and ground TSVs is accurately modeled and analyzed for both static and high-frequency situations. Furthermore, the impact of substrate admittance on the capacitance-voltage dependence is explored. Parametric studies are performed to study the effects of different physical and material parameters on the coupling capacitance, which include TSV radius, liner thickness, doping concentration, amount of oxide charges, and work function of TSV filling materials. Based on the proposed model, the nonlinear effect of the coupling capacitance on transient noise is examined and explained.National Basic Research Program of China [2015CB0572]; Importation and Development of High-Caliber Talents Project of Beijing Municipal Institutions, Great Wall Scholar [CITTCD20150320]; National Natural Science Foundation of China [61176102]; Collaborative Project of the National Center for Advanced Packaging, ChinaSCI(E)[email protected]; [email protected]; [email protected]; [email protected]
High Frequency Analysis and Characterization of TSVs for High-Speed Integrated Systems
No full textThree-dimensional integration technology is deemed as the most promising alternative in post Moore's Law era. The electrical performance of through silicon vias (TSVs), which are the key enabler for 3D integration, is crucial to modeling and design of 3D systems, especially for high-speed systems. This paper gives a partial review on recent progress in the field with the focus on the high-frequency analysis and characterization.CPCI-S(ISTP)[email protected]; [email protected]; [email protected]; [email protected]; [email protected]
High Speed Test Structures for In-line Process of 3D System in Packaging
No full textAs the requirement of portable and smart devices rapidly increasing, applications of high performance 3D integration and M/NEMS packaging have enormous market potential. High speed in-line testing is a critical bottleneck for 3D SiP and TSV processes. In this paper, we promote a method of in-line testing for interconnection performance of TSV structures, and a novel 3D CPW model for performance testing is introduced. The S parameters and Z parameters are simulated respectively. To determine the optimum TSV diameter and sidewall thickness, different types of the model have been analyzed. During our experiments, a typical structure for high frequency performance testing was fabricated successfully. The results were compared with related simulations. By using this method, the high frequency performance testing of TSV can be achieved.Engineering, Electrical & ElectronicEICPCI-S(ISTP)
Study of TSV Leakage Current and Breakdown Voltage
No full textThree potential contributing factors to the TSV leakage and breakdown are discussed and analyzed in this study. In addition, an in-line testing methodology is put forward so that leakage and breakdown data could be easily obtained. Finite element method simulation was used to illustrate the testing principle, and experimental test were carried out for validation. It was found that the most contributing factor to the TSV leakage and breakdown is the uniformity of the insulator layer thickness, while via-diameter and pitch between TSVs are factors of failure mechanism of the low-frequency characteristics.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000349907100105&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701Engineering, Electrical & ElectronicEICPCI-S(ISTP)
A Thick Film Accelerometer based on L TCC-Technology
No full textThis paper reports a thick film accelerometers based on LTCC technology, The authors introduce a LTCC compatible design and develop a fabrication process flow of this new kind of accelerometer, and moreover, samples for testing are fabricated, It is designed as a piezoresistive accelerometer, which consists of a proof mass, two parallel leaf springs, and a fixed frame. The sensing device may be embedded in the LTCC substrate. The piezoresistive signals are transmitted through LTCC multilayer interconnection and input to a DC amplifier which is surface-mounted to the substrate. The mechanical and electrical characterizations have been accomplished by simulation.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000319836000210&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701Engineering, Electrical & ElectronicCPCI-S(ISTP)
In-line Testing of Blind TSVs for 3D IC Integration and M/NEMS Packaging
No full textAn in-line testing procedure of blind TSVs is put forward in this study. Insulation integrity is chosen to determine the eligibility. It is to probe the upper end of two or more neighboring TSVs during the manufacturing right after the blind vias being formed. Finite element method simulation was used to illustrate the testing principle, and experimental test were carried out for validation. During the test, leakage current data between two blind vias is obtained and I-V characteristic curve is plotted. It can be determined whether or not the TSVs are qualified.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000327183000045&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701Engineering, BiomedicalEngineering, Electrical & ElectronicNanoscience & NanotechnologyEICPCI-S(ISTP)
