1,720,976 research outputs found
Procedimento e sistema per il calcolo del prodotto interno su campi di Galois
No full textCircuit for the inner or scalar product computation in Galois field
Robust synchronization in SO(3) and SE(3) via low-rank and sparse matrix decomposition
Full text linkThis paper deals with the synchronization problem, which arises in multiple 3D point-set registration and in structure-from-motion. The problem is formulated as a low-rank and sparse matrix decom- position that caters for missing data, outliers and noise, and it benefits from a wealth of available decomposition algorithms that can be plugged-in. A minimization strategy, dubbed R-GoDec, is also proposed. Experimental results on simulated and real data show that this approach offers a good trade-off between resistance to outliers and speed
Efficient finite field digit-serial multiplier architecture for cryptography applications
No full textCryptographic applications in embedded systems for smart-cards require low-latency, low-complexity and low power dedicated hardware. In this work the GBB algorithm for finite field multiplication is optimised by recoding and the related digit-serial VLSI multiplier architecture is designed and evaluated
Comparative cost/performance evaluation of digit-serial multipliers for finite fields of type GF(2n)
No full textMultiplication in finite fields (Galois fields) is a basic operation for cryptography applications. Recent proposals for elliptic code cryptography, require efficient computation of multiplication in finite fields of type GF(2n) for large values of n (150, 200 bits). Digit-serial multiplier VLSI architectures are an attractive solution, being a compromise between purely parallel and serial ones. A comparative study of digit-serial multiplier VLSI architectures, for fields of type GF(2n), is carried out. Such architectures are reviewed, some further optimisations are proposed, and are then implemented in VHDL (CMOS cell library, 0.35 μm, by ST Microelectronics). Figures of merit like time latency, silicon area and power consumption are evaluated by simulation with Synopsis tools, varying parameters like the size n of the field elements and the size k of the blocks of bits being processed in parallel by the digit-serial architectures
Robust localization in wireless sensor networks via low-rank and'sparse matrix decomposition
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About the performances of the advanced encryption standard in embedded systems with cache memory
No full textModem networked embedded systems represent a growing market segment in which security is becoming an essential requirement. The Advanced Encryption Standard (AES) specification is becoming the default choice for such type of systems; however, a proper software implementation of AES is of fundamental importance in order to achieve significant performance. Current implementations presented in the literature differ in terms of the amount of look-up tables used for precomputing the functions of the encryption/decryption phase. This raises some questions regarding which AES implementation is optimal for a specific system configuration that, up to now, has been only empirically solved. In this work, we present an analytical model to study and evaluate the performance of the possible AES implementations in the early phases of system development. We then show that the proposed high-level timing model captures, with significant accuracy, the actual performance of current AES applications and thus it can be used for the early evaluation of optimal AES implementations and to support the design space exploration phase. Validating experiments have been carried out on the Lx architecture, a scalable and customizable VLIW architecture developed by STMicroelectronics and HP Labs. Some final considerations are eventually reported about the relevant characteristics of the analyzed implementations and the role of the cache memory
Procedimento e sistema per la implementazione dell'algoritmo AES
No full textMethod and circuit for data encryption/decryptio
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