1,721,342 research outputs found
Compilatori Principi, tecniche e strumenti - 2/Ed
No full textcuratela alla traduzione del libro americano Compilers, 2/ed di Alfred V. Aho, Monica S. Lam, Ravi Sethi, Jeffrey D. Ullman.
In Italiano: Compilatori Principi, tecniche e strumenti - 2/Ed. 2009 pp. 936, Pearson ora Pearson Paravia Bruno Mondadori S.p.A
Sistemi Operativi, 3/ed
No full textCuratela della traduzione in Italiano di Traduzione in italiano. Sistemi Operativi, 3 ed, Pearson Education Italia. Versione in lingua inglese: Operating Systems, third Edition, Prentice Hall, Pearson Education, New Jersey, USA, 2004. ISBN 0-13-124696-8
ScaDL 2022 Invited Talk 1: Design of secure power monitors for accelerators, by exploiting ML techniques, in the Euro-HPC TEXTAROSSA project
No full textThe evolution of High Performance Computing (HPC) has to face with several obstacles, including power/thermal management of the cores and the presence of heterogeneous computing platforms. Within the Euro-HPC project TEXTAROSSA, started in spring 2021, several HPC applications exploiting AI and with the need of processing big chunks of data in a secure context, are properly accelerated by leveraging ad-hoc designed accelerators to be implemented in hardware. Such customized heterogeneity of execution has many benefits, but increases the problem of power management, since the accelerators, possibly generated through high-level-synthesis, are neither providing run-time information on their power consumption, nor allows to control the security of the information flow against implementation attacks. In such scenario, any global power manager / resource orchestrator, can operate only with a partial picture of the overall systems and not in real-time, with the risk of being trapped in poor power optimizations and unbalanced resource exploitation. The goal of the talk is to show how is possible to exploit popular ML techniques for a twofold purpose: •Automatically generate an on-line power monitor, to augment the hardware description of any piece of hardware, in particular that of cores and accelerators, capable to provide on-line power estimated in less that few milliseconds. •Select, in the space of all the possible power monitors, those that are not leaking information that can be used to mount side-channel attacks
Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators
Full text linkNetworks-on-chip (NoCs) are a widely recognized viable interconnection paradigm to support the multi-core revolution. One of the major design issues of multicore architectures is still the power, which can no longer be considered mainly due to the cores, since the NoC contribution to the overall energy budget is relevant. To face both static and dynamic power while balancing NoC performance, different actuators have been exploited in literature, mainly dynamic voltage frequency scaling (DVFS) and power gating. Typically, simulation-based tools are employed to explore the huge design space by adopting simplified models of the components. As a consequence, the majority of state-of-the-art on NoC power-performance optimization do not accurately consider timing and power overheads of actuators, or (even worse) do not consider them at all, with the risk of overestimating the benefits of the proposed methodologies. This article presents a simulation framework for power-performance analysis of multicore architectures with specific focus on the NoC. It integrates accurate power gating and DVFS models encompassing also their timing and power overheads. The value added of our proposal is manyfold: (i) DVFS and power gating actuators are modeled starting from SPICE-level simulations; (ii) such models have been integrated in the simulation environment; (iii) policy analysis support is plugged into the framework to enable assessment of different policies; (iv) a flexible GALS (globally asynchronous locally synchronous) support is provided, covering both handshake and FIFO re-synchronization schemas. To demonstrate both the flexibility and extensibility of our proposal, two simple policies exploiting the modeled actuators are discussed in the article
A SPICE-Based Approach to Steady-State Circuits Analysis
No full textA new SPICE‐based approach for steady state circuit analysis is presented which uses SPICE computational capabilities and a master programme to carry out the periodic response. the master programme implements a suitable method for steady state analysis and is linked with SPICE only via I/O SPICE files. This allows the use of all SPICE analyses together with the new one simply by adding a new statement in the input SPICE file. In this paper the bases of this technique, including the chosen steady state method and the whole system structure, are discussed. Simulation results produced by this technique have been compared, by means of two meaningful examples, with those obtained both by SPICE and by a dedicated simulator for steady state analysis working in the frequency domain
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