1,721,155 research outputs found
Informatica per Ingegneria Gestionale
No full textSi tratta del testo per il corso di Informatica per Ingegneria Gestionale, prodotto dall'autore tramite la piattaforma Create della McGraw Hill, selezionando il materiale pertinente il corso da alcuni testi (di altri autori) della McGraw Hill
Hipeac Network of Excellence N. IST-004408 Deliverable D3.b - Report on Research Results. NoC characterization and deployment in mono and multiprocessor systems
No full textHipeac Network of Excellence N. IST-004408 Deliverable D3.b - Report on Research Results. Cluster 442 - Adaptable Computers for Embedded Applications 2
No full textAn algorithm for the Classification of Coherence Related Overhead in Shared-Bus Shared-Memory Multiprocessors
No full textThis paper describes an algorithm for the classification
of coherence overhead in shared-bus shared-memory
multiprocessors. This algorithm is applicable to Write
Update, Write Invalidate and Hybrid protocols and models
the effect of finite size (real) cache. It differs from previous
classifications because it classifies any sources of
coherence overhead, i.e. invalidation miss, invalidate and
write transactions, and also classifies the sharing due to
process migration, namely passive sharing. A validation
has been carried out considering SPLASH benchmark, and
sample results in the case of E-Commerce Server are given
Exploiting Replication to Improve Performances of NUCA-Based CMP Systems
Full text linkImprovements in semiconductor nanotechnology made chip multiprocessors the reference architecture for high-performance microprocessors. CMPs usually adopt large Last-Level Caches (LLC) shared among cores and private L1 caches, whose performances depend on the wire-delay dominated response time of LLC. NUCA (NonUniform Cache Architecture) caches represent a viable solution for tolerating wire-delay effects. In this article, we present Re-NUCA, a NUCA cache that exploits replication of blocks inside the LLC to avoid performance limitations of D-NUCA caches due to conflicting access to shared data. Results show that a Re-NUCA LLC permits to improve performances of more than 5% on average, and up to 15% for applications that strongly suffer from conflicting access to shared data, while reducing network traffic and power consumption with respect to D-NUCA caches. Besides, it outperforms different S-NUCA schemes optimized with victim replication
Extension of Web Server Systems for E-Commerce: Incremental Crowding vs. Functional Doubling-Up
No full textTowards Relating Physiological Signals to Usability Metrics: A Case Study with a Web Avatar
Full text linkInferring the user’s approval of a graphical interface with non-invasive devices can be effective in improving its design and in implementing adaptive pleasant interactions. This paper investigates how 3 common physiological signals, i.e. skin conductance, heart rate and respiration, can be exploited to infer users’ approval of an online avatar embedded in a health care Website. A between group experiment is performed with participants who have the avatar support and participants who do not. During the experiment, skin conductance, hearth rate and respiration were monitored, together with traditional usability metrics (visited pages, completion times, errors, etc). At the end of each experiment, a feedback questionnaire is proposed to infer information related to the user experience, ease of use and approval. Results indicate that the respiration overshoot rate is closely related to the users’ appreciation of the avatar based interaction. Further steps of our research will consider improvements in the results by investigating and exploiting mutual effects induced by the multiple collected signals
Hipeac Network of Excellence N. IST-004408 Deliverable D3.b - Report on Research Results. Cluster 1150 - Adaptable Computers for Embedded Applications
No full textHigh Performance Embedded Architectures and Compilers 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings
No full textTransactions on High-Performance Embedded Architectures and Compilers - Special Issue on Memory Performances
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