1,720,978 research outputs found
A VHDL Error Simulator for Functional Test Generation
No full textThis paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. All components of the simulation environment are automatically built starting from the VHDL specification of the description under test. The effectiveness of the simulator has been measured by using a random functional test generator. Functional test patterns produce, on some benchmarks, a higher gate-level fault coverage than the fault coverage achieved by a very efficient gate-level test pattern generator. Moreover, functional test generation requires a fraction of the time necessary to generate test at the gate level. This is due to the possibility of effectively exploring the test patterns space since error simulation is directly performed at the VHDL level
Genetic Algorithms: the Philosopher’s Stone or an Effective Solution for High-Level TPG?
No full texttesting and G
Laerte++: an Object Oriented High-Level TPG for SystemC Designs
No full textThis paper describes Laerte++, a high-level test pattern generator (TPG) for SystemC designs. All necessary features of a high-level TPG (e.g., fault models definition, hierarchical analysis, coverage measurements, etc.) are implemented by exploiting native SystemC characteristics funded on OO principles. The framework robustness and extensibility are guaranteed by an accurate use of software engineering methodologies for the Larte++ classes definition and an extensive use of the Standard Template Library (STL) for data structure definition. Laerte++ allows to set up and run an ex-novo TPG session by adding very few C++ code lines to any SystemC design under test description. The applicability and the efficiency of the presented framework have been confirmed by the analyzed benchmarks
AMLETO: A Multi-language Environment for Functional Test Generation
No full textMore and more people are starting to use the SystemC description language to model and simulate new designs. This is due mainly to the simplicity and power of the language. The number of models written in SystemC currently available is still very limited and testing SystemC descriptions is still an open issue, since the language is new and researchers are looking for efficient error models and coverage metrics. This paper presents AMLETO, a multi-language environment developed to efficiently test embedded systems and IP-Cores. Using IIR, an HDL language independent representation, it supplies: fast translation from VHDL to SystemC of design descriptions and viceversa, generation and setup of customized TPGs for the design under test and generation of erroneous models capable of simulating the presence of design error
Soft-Cores Generation by Instruction Set Analysis
No full textThe popularity of Soft Cores is rapidly increasing. Their integration in a design requires their synthesis and optimization, thus their application is more complex than the use of Hard Cores. However, Soft Cores can be customized to the design constraints, thus promising to lead to more efficient designs. The decision of using Soft or Hard Cores is difficult since it is a trade-off between performance, cost and design time. The parametrization methodology presented in this paper gives to the Soft Core providers the possibility of putting on the market easily customizable versions of their Cores. Moreover, the proposed Soft-Cores generator helps the designer to select between the Soft and the Hard-Core version of a processor
The Use of SystemC for Design Verification and Integration Test of IP-Cores
No full textThe current trend of systems on silicon is leading to System-on-Chips with embedded software and hardware components. Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct integration in a design implies more complex verification problems. The SystemC language allows one to create and integrate accurate models of software algorithms, hardware architectures and interfaces for SoCs. In this paper, characteristics of the language are exploited to define a design verification framework for integration-test of IP-cores. Intellectual property of cores is guaranteed by adopting-a client/server simulation architecture and by allowing functional test generation on faulty IP-core models without disclosing their internal structure. Moreover, the methodology can be applied to mixed descriptions based on VHDL and SystemC, since an abstraction layer has been defined allowing clients and/or servers to be indifferently described in VHDL or SystemC
A Fault Tolerant Incremental Design Methodology
No full textIncremental design is the widest applied methodology for VLSI design since, it allows one to produce early versions of the system that, even if not satisfying all requirements, allow one to verify its applicability in the field. The migration from, a system version to a more powerful one is based on the substitution of a module with a more powerful module, which implements new features. This upgrade can introduce errors, which are difficult to be identified during the design since the standard concept of equivalence checking cannot be applied in this context. In fact, the original and the redesigned module can implement different specifications or can achieve the same results under different timing constraints. The paper analyzes this problem and proposes a fault tolerant incremental design methodology able to reduce or avoid such errors
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