1,721,062 research outputs found
Injection Locked Oscillators for Quadrature Generation at Radio Frequency
No full textThe design of quadrature signal generators is one of the most challenging issues in modern RF transceivers. After a brief review of conventional techniques, this paper presents injection locked oscillators as a viable alternative to achieve high performance and low power consumption. Two different architectures, realized in a 0.18 μm CMOS technology, are presented and compared. The first shows excellent driving capability and simple design, the second lends itself to low power operation
A 1.8-GHz Injection-Locked Quadrature CMOS VCO With Low Phase Noise and High Phase Accuracy
No full textInjection-locked quadrature voltage-controlled oscillators are introduced in this paper as high accuracy, low phase noise, and low-power I and Q generators. A master voltage-controlled osciflator (VCO), running at twice the output frequency, locks two coupled VCOs. The former determines phase noise while the latter sets phase accuracy, thus, breaking the tradeoff between the two parameters, the main limit of free running coupled VCOs, recently proposed in the framework of highly integrated solutions. The proposed design has been tailored to DCS 1800 and prototypes have been fabricated in a 0.18-mu m CMOS technology. Experiments show a phase noise of -127 dBc/Hz and -139 dBc/Hz at 600 kHz and 3 MHz, respectively, while consuming 10 mA from 1.8 V supply. A 185-dB state-of-the-art phase noise figure of merit results. Accuracy between output signals is determined by means of image band rejection (HIR) measurements on a purposely developed single-side-band upconversion mixer. Minimum IBR among 20 samples is as large as 46 dB
CMOS injection locked oscillators for quadrature generation at radio-frequency
No full textThe design of quadrature local oscillators for CMOS wireless transceivers is still one of the most challenging issues. This paper focuses the advantages of injection locking techniques to achieve high-performance quadrature generators. A synchronizing oscillator sets spectral purity while locked oscillators set quadrature accuracy and drive the mixer LO input capacitances. Two different architectures, realized in a 0.18 mu m CMOS technology, are illustrated and compared. The first, using LC tank locked oscillators as frequency dividers, is tailored to UNITS and show high driving capability with low power. Simple and accurate equations for the design are reported. The second quadrature generator, employing coupled VCOs driven by an auxiliary VCO, is tailored to DCS1800 and achieves outstanding phase accuracy and phase noise. Experimental results compare favorably against previously published solutions. (c) 2006 Elsevier Ltd. All rights reserved
Injection Locked Coupled VCOs for Low Phase Noise and HighAccuracy Quadrature Generation
No full textCoupled VCOs for quadrature generation allow very accurate 90' phase shifted output signal but suffer from a trade-off between phase noise and phase accuracy, leading to poor noise times power product. In this work, we propose to synchronize them by means of an additional VCO. In this way, the coupled VCOs guarantee the quadrature accuracy between output signals, whereas the synchronizing VCO sets phase noise. The design istailored to a DCS-1800 system. Prototypes, realized in a 0.18pm CMOS technology, show the following: 285MHz tuning band, 45dB minimum Image Band Rejection, -127 dBc/Hz Phase Noise at 600kHz offset while drawing l0mA from 1.W. The Phase Noise figure of merit is 185dB, 20dB better than free running quadrature VCOs
Balanced CMOS LC-tank Analog Frequency Dividersfor Quadrature LO Generation
No full textA regenerative circuit based on an LC-tank balanced divider is proposed in this paper for quadrature LO signal generation. For given tank quality factor, it provides larger operation bandwidth and improved quadrature accuracy when compared with conventional injection locked frequency dividers. The operation bandwidth can be adjusted dynamically simply regulating the biasing current. Experimental results, carried on 0.18 μm CMOS prototypes, show 42% range with a tank quality factor of 13.5 while driving 1.5pF output capacitance. At the band edge, biasing current is 8mA. Quadrature accuracy has been verified through the achievable image rejection of a purposely developed single side band up-converter. Measurements, performed on five samples, show a minimum image rejection of 44dB.A regenerative circuit based on an LC-tank balanced divider is proposed in this paper for quadrature LO signal generation. For given tank quality factor, it provides larger operation bandwidth and improved quadrature accuracy when compared with conventional injection locked frequency dividers. The operation bandwidth can be adjusted dynamically simply regulating the biasing current. Experimental results, carried on 0.18μm CMOS prototypes, show 42% range with a tank quality factor of 13.5 while driving 1.5pF output capacitance. At the band edge, biasing current is 8mA. Quadrature accuracy has been verified through the achievable image rejection of a purposely developed single side band up-converter. Measurements, performed on five samples, show a minimum image rejection of 44dB. © 2005 IEEE
Analysis and Design of Injection-Locked LC Dividers for Quadrature Generation
No full textInjection-locked LC dividers for low-power quadrature generation are discussed in this paper. Modeling the circuits as regenerative frequency dividers leads to very simple analytical expressions for the locking band, phase deviation from quadrature and phase noise. Maximizing the ratio between the injected and the biasing current is beneficial to all the above parameters whereas reducing the tank quality factor improves locking band and quadrature accuracy, though at the expense of current consumption, for given output amplitude. To validate the theory, experiments have been carried on a 0.18-mum CMOS direct conversion IC, embedding an injection-locked quadrature generator, realized for the Universal Mobile Telecommunication System. Frequency locking range as large as 24% and phase deviation from quadrature around 0.8degrees are measured while each divider consumes 2 mA. The phase noise of the quadrature generator is determined by the driving oscillator phase noise because the dividers contribution is easily made negligible up to hundreds of megahertz offset
Serendipitous noise reduction in inductively degenerated CMOS RF LNAs
No full textDesigners of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the-art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used
CMOS Balanced Regenerative Frequency Dividers for Wide Band Quadrature LO Generation
No full textCMOS regenerative frequency dividers, based on a fully balanced Gilbert cell, are analyzed in this paper for quadrature local oscillator (LO) signal generation. Driven in opposite phase by double frequency signals, they provide quadrature waveforms while simultaneously driving large mixers LO input capacitances, thereby avoiding power hungry buffers typically required. Experimental results, carried out on 0.18 mm CMOS prototypes, show 68% bandwidth around 2GHz center frequency, with a quadrature accuracy better than 11, making them suitable for multi-standard wireless receivers. To keep the output amplitude constant while simultaneously minimizing the average power consumption, a digital calibration loop regulates each divider biasing current
A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS
No full textA sub-harmonic architecture for wireless signal processing at Ka band is proposed resulting in IC power saving because the LO circuits operate at half frequency and no IF stage is necessary. A 65nm CMOS prototype, including High Frequency front-end, base-band amplifier and multi-phase VCO and dividers, shows: 31.5dB gain, 6.5dB NF, -17dBm IIP3, -90dBm LO re-irradiation at 24GHz, while consuming 92mW
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