1,720,976 research outputs found
A PLL-based frequency synthesizer for 160-MHz double-sampled SC filters
No full textThis paper describes a clock generator for a double-sampled switched capacitor (SC) filtering system. The circuit is based on a fast charge-pump phase-locked loop (PLL) system that multiplies an external reference clock signal by a factor of eight and also ensures a high precision and stability of two internal nonoverlapped clock phases up to 80 MHz. This allows the driving of double-sampled SC filters up to 160 MHz sampling rate. The PLL is a third-order system with a bandwidth of 100 kHz and a lock-in time of 15 μs. The output clock jitter is 170 ps r.m.s. The total power consumption at 160 MHz is 25 mW and the total chip area is about 1 mm
Transconductor circuit with high-linearity double input and active filter thereof
No full textThe invention relates to a transconductor circuit with a double input and a single output, comprising two input transistors (M1, M2) whose primary conduction terminals (D1, S1, D2, S2) are respectively connected together; in this way, variations in load current and voltage can be made lower, thereby also lowering distortion from changes in their transconductance
Method for erasing a common mode current signal and transconductor assembly using such method
No full textA low-voltage transconductor circuit in which the common mode gain of a first transconductor stage is compensated by a second transconductor stage (connected in parallel with the first transconductor stage) which has no differential mode transconductance, and which is connected so that its common mode transconductance offsets the common mode transconductance of the stage. This greatly reduces the common mode current signal at the output, while avoiding the necessity for a current sink at the source of the input transistors
A 3 V 12-55 MHz BiCMOS pseudo-differential continuous-time filter
No full textThe reduction of the supply voltage forces one to develop system and circuit solutions able to achieve the same performance previously obtained with higher supply voltage. In this paper, a second-order low-pass continuous-time filter operating at a 3 V power supply is presented. The prototype filter is implemented using a highly linear pseudo-differential transconductor. The input common-mode signal is canceled at the transconductor level using a feed-forward path. The output common mode voltage is controlled at the filter level using lossy integrators. A prototype cell has been realized in 1.2 μm BiCMOS technology. The pole frequency can be tuned in the range 12-55 MHz. A THD of -40 dB is achieved for signals up to 1 Vpp at 10 MHz. The dynamic range is approximately 60 d
A 70-mW seventh-order filter with 7-50 MHz cutoff frequency and programmable boost and group delay equalization
No full textA seventh-order phase equiripple continuous time filter implementing pulse shaping and noise filtering for partial response maximum likelihood (PRML) read channel applications is presented. The 7-50 MHz cutoff frequency, amount of boost, and group-delay slope are programmable via 7-b digital-to-analog converters (DAC's). At 50 MHz fc, power consumption is 70 mW and output swing for 1% distortion is more than 500 mVpp. The transconductance capacitance (Gm-C) filter is built in a 0.7-μm 10-GHz BiCMOS technolog
Transconductor stage
No full textA transconductor stage for high-frequency filters of a type which comprises an input circuit portion having signal inputs and an output circuit portion, incorporates a pair of field-effect transistors having respective gate and source terminals in common, and has the output portion formed of a pair of bipolar transistors connected to the aforesaid field-effect transistors
Low-power BiCMOS continuous-time shaping filter
No full textA biquadratic continuous-time filter designed to operate as signal shaper in the read-out electronics of elementary particles experiments has been implemented in 2 μm BiCMOS technology. The cell synthesizes a semi-Gaussian response with a shaping time adjustable in the range 18-30 ns. The power consumption is 1.25 mW from a single 5 V power supply. The integral nonlinearity is within 1% for an input signal amplitude up to 200 mV. The chip active area is 0.08 mm2. The measured input referred noise is 50 nV/√H
Low-voltage analog filters
No full textThis paper reviews the design of analog filters at low supply voltage. In particular, the main focus is on switched capacitor and g m-C type filters because, at the present time, they have the greatest commercial importance. SC implementations are discussed in the context of low frequency high precision applications while gm-C implementations are discussed in the context of high frequency medium/low precision applications. Both fundamental and practical limitations to the achievable dynamic range at low supply voltage are explained. The paper reviews well established circuit and architectural techniques as well as some promising new ones that might result in performance improvements in the futur
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