1,721,155 research outputs found
A hierarchical test generation approach for large controllers
No full textA testing approach targeted at Hardware Description Language (HDL)-based specifications of complex control devices is proposed. For such architectures, gate-level test pattern generators require insertion of scan paths to enable the flat gate-level representations to be efficiently handled. In contrast, we present a testing methodology based on the hierarchical finite state machine model. Our approach allows the generation of compact test sets with very high stuck-at fault coverages, without any design-for-testability logic other than hardware reset. This method can be used any time the functional information is available together with the gate-level structural description. High fault coverages are achieved with smaller test lengths and execution times with respect to state-of-the-art gate-level test pattern generator
TIES: A testability increase expert system for VLSI design
No full textTIES is a knowledge based system that advises the ICs designer on the best modifications to perform on a circuit with testability problems, while satisfying design constraints defined by the user. The proposed approach differs from previous papers for three main reasons. The DfT techniques are applied only to critical areas of the circuit which are identified by means of a testability measure. A powerful description of design for testability techniques in the knowledge base is adopted. Moreover, a new decision scheme for the comparison among different implementations is proposed
Automatic Generation of Error Control Codes for Computer Applications
No full textThis paper proposes a methodology, implemented in a tool, to automatically generate the main classes of error control codes (ECC's) widely applied in computer memory systems to increase reliability and data integrity. New code construction techniques extending the features of previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes have been integrated in the tool. The proposed techniques construct systematic odd-weight-column SEC-DED-SBD codes with odd-bit-per-byte error correcting (OBC) capabilities to enhance reliability in high speed memory systems organized as multiple-bit-per-chip or card
Functional Fault Models and Gate Level Coverage For Sequential Architectures
No full textThis paper introduces and evaluates functional fault models for test pattern generation of sequential circuits at the finite state machine level. Evaluation of the proposed fault models against their gate level fault coverage on multi-level implementations is presented. The relationships between functional and gate level fault coverage are discussed
A Complete Testing Strategy Based on Interacting and Hierarchical FSMs
No full textControl-dominated architectures are usually specify, in a hardware description language (HDL), by means of a composition of FSMs. This paper presents two FSMs based models which can be extracted from a Statechart or a HDL description. Such models are compared to the description of the device at the different abstraction levels of a standard synthesis pow. This comparison simplifies the testing problem producing a complete testing strategy that uses functional information to perform scan insertion, redundancies removal and test pattern generation even for such devices which cannot be satisfactorily analyzed at the gate level
An extended-UIO-based method for protocol conformance testing
No full textVerification of protocols is performed through conformancetesting. The aim of this paper is to introduce the conformance test generation approach for protocols described by means of Finite State Machines. A functional fault model is adopted and the state discrimination is performed by applying an extended version of Unique Input Output Sequences (UIO), which, different from classical UIO, can always be found in any state. Both algorithms for efficient extendedUIO sequence identification and for optimal test sequence generation are presented, together with the experimental results on different protocol descriptions
VHDL testability analysis based on fault clustering and implicit fault injection
No full textTestability analysis of VHDL sequential models is the main topic of this paper. We investigate the possibility to obtain information about the testability of a sequential VHDL description before its actual synthesis. The analysis is based on an implicit fault model that injects faults into a BDD based description extracted from the VHDL representation. Such an injection is related to the original VHDL representation thus allowing the identification of potential testability problems before RTL and logic synthesis. Fault injection is performed efficiently by exploiting the concept of fault clustering, that is the possibility of grouping faults and analyzing them concurrently. The proposed methodology is applied to benchmarks for efficiency evaluation and to a real VHDL descriptio
FSM fault models impact on test performances
No full textAim of this paper is the analysis of different functional fault models for multi-level implementations of sequential circuits. The relationships between functional and gate level fault coverage are fully discussed
The use of hierarchical information to test large controllers
No full textGate-level test pattern generators require insertion of scan paths to handle the flat gate-level representation of a large sequential controller. In contrast, we present a testing methodology based on the hierarchical finite state machine model. Such a model is used to specify very complex control devices by means of a top-down design approach. Our approach allows the generation of compact test sets with very high stuck-at fault coverages, without any DfT logic
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