1,721,042 research outputs found
Behavioral Test Generation for Test Embedding
No full textBehavioral Test Generation for Test Embeddin
VHDL Testability Analysis based on Faults Clustering and Implicit Faults Injection
No full textestability analysis of VHDL sequential models is the main topic of this paper. We investigate the possibility to obtain information about the testability of a sequential VHDL description before its actual synthesis. The analysis is based on an implicit fault model that injects faults into a BDD based description extracted from the VHDL representation. Such an injection is related to the original VHDL representation thus allowing the identification of potential testability problems before RTL and logic synthesis. Fault injection is performed efficiently by exploiting the concept of fault clustering, that is the possibility of grouping faults and analyzing them concurrently. The proposed methodology is applied to benchmarks for efficiency evaluation and to a real VHDL description
Symbolic Optimization of FSM Networks Based on Redundancies Identification and Removal
No full textThis paper presents a binary decision diagram (BDD)-based algorithm for the optimization of the driven machine, 2, of a finite-state machine (FSM) network with cascade connection, 1 2. The technique we propose relies on redundant faults identification and removal. A fault, , located into machine 2, is redundant with respect to the overall network if the driving machine 1 is not able to generate any test sequence for such a fault. When the state transition graph (STG) specifications of the network components are available, the standard way for checking the redundancy condition for the considered fault requires to first construct the product machine 2 2 , where 2 is the faulty FSM, then to connect it to the driving machine, and finally to perform reachability analysis on the composed machine 1 2 2 . Clearly, the size of such machine limits the applicability of the approach above to systems whose components have a few tens of states at most, even when symbolic traversal algorithms are used. Since we are interested in dealing with networks of larger FSM’s (i.e., machines whose STG’s can not be represented explicitly), we propose to use the product automaton = 1 , where 1 is the finite automaton (FA) accepting all the output sequences of 1, and is the FA accepting all the test sequences for fault , instead of machine 1 2 2 . This simplifies sensibly the task of the reachability analysis program, since has considerably less states and less edges than the product machine 2 2 and, thus, the size of the BDD representation of its transition relation is much more easily manageable. In addition, differently from other approaches, automaton 1 is not required to be deterministic and state minimal. This allows us to avoid the application of determinization and state minimization procedures whose complexity is exponential. We present experimental results for examples (i.e., network of interacting controllers) on which existing optimization methods are not applicable, due to the size of the component FSM’s. We also provide a comparison to the data produced by state-of-the-art FSM network optimizers on small benchmarks in order to show the effectiveness of our approach
Implicit Testability Techniques for VHDL Based ASIC Design
No full textImplicit Testability Techniques for VHDL Based ASIC Desig
A Testing Methodology for VHDL Based High-Level Designs
No full textThe test problem increasingly affects system design process, related costs and time to market. Requirements from VLSI/WSI manufacturers are for fast and reliable testabilit y tools, with the possibilit y of their introduction in early phases of design. In this paper we describe the different abstraction levels at which testabilit y analysis will be applied in the REQUEST Project. The global tool-set architecture supporting this analysis will be introduced and commented. All design phases are included in this design flow, from the Data Flow Graph/Control Flow Graph (CDFG/CFG) representations of behaviors (directly derived from VHDL behavioral specifications), down to gate level. The paper will t hen present an application scenario for the behavioral level, where most of the innovative features have been introduced, including a new behavioral fault model strictly related to the lower levels of abstraction
The Request Testability Methodology for VHDL Based ASIC Design
No full textThe Request Testability Methodology for VHDL Based ASIC Desig
An Extended Testing Methodology for VHDL Based High-Level Design
No full textAn Extended Testing Methodology for VHDL Based High-Level Desig
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