1,721,220 research outputs found
Systolic Arithmetic Architectures
No full textIn this paper parallelism on the algorithmic, architectural, and arithmetic levels is exploited in the design of a Residue Number System (RNS) based architecture. The architecture is based on modulo processors. Each modulo processor is implemented by two dimensional systolic array composed of very simple cells. The decoding stage is implemented using a 2-D array, too. The decoding bottleneck is eliminated. The whole architecture is pipelined which lead to high throughput rate.http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=65808
Choosing System Moduli For Rns Arithmetic Processors
No full textDesigning an optimal Residue Number System (RNS) processor in terms of area and speed depends on the choice of the system moduli. In this paper an optimal algorithm for choosing the system moduli is presented. The algorithm takes into consideration several constraints imposed by the problem definition. The problem is formalized as an integer programming problem to optimize an area/time objective function.http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=60085
Formal Verification Of Systems On Chips: Current & Future Directions
No full textAs we do not have a preprint copy of this article we cannot legally post it, so please use this record to request the article via interlibrary loan from your home library or you can find the final publication available from Springer by the link below.In this tutorial we present the area of formal verification of systems on Chips. The paper discuss the following topics: different approaches of formal logic such as first order logic, high order logic, temporal logic. A case study of object-oriented paradigm is presented. A survey of the current research status in presented. The paper concludes with a section on the future directions.http://link.springer.com/chapter/10.1007%2F978-1-4615-0351-4_
A Formal High Level Synthesis Approach For DSP Architectures
No full textIn this paper, we introduce a novel approach for high level synthesis for DSP algorithms. Two features are provided by the approach: completeness and correctness. A given algorithm will be represented in a new developed language termed Algorithm Specification Language (ASL). ASL has the ability to describe any general algorithm. An automatic procedure is used to transform an ASL representation into a specific realization specification using a correctness preserving set of transformations. The realization format is based on representing the digital architectures by another developed language called Realization Specification Language (RSL). Logic Programming is used as a user interface for the synthesis procedure.http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=11598
Hoover: Hardware Object-Oriented Verification
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In this paper a new formal hardware verification approach based on object oriented techniques is presented. The HOOVER system (Hardware Object Oriented VERification) is described. A cell library of different hardware components has been implemented as classes. Components in the cell library are described at the transistor level, gate level, logical level, and functional level. The verification of a CMOS inverter and 1-bit CMOS adder using HOOVER is given in the paper.http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=665308&tag=
Fast And Flexible Architectures For Rns Arithmetic Decoding
No full textAn implementation of a fast and flexible residue decoder for residue number system (RNS)-based architectures is proposed. The decoder is based on the Chinese Remainder Theorem (CRT). It decodes a set of residues to its equivalent representation in weighted binary number system. This decoder is flexible since the decoded data can be selected to be either unsigned magnitude or 2's complement binary number. Two different architectures are analyzed; the first one is based on using carry-save adders (CSA's), while the other is based on utilizing modulo adders (MA). The implementation of both architectures is modular and is based on simple cells, which leads to efficient VLSI realization. The proposed decoder is fast; it has a time complexity of O(log N ) ( N is the number of moduli).http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=13657
Network Traffic Characterization For High-Speed Networks Supporting Multimedia
No full textContinuously growing needs for distributed applications that transmit massive amount of data has led to the emergence of high-speed networks that require broadband and multimedia capabilities. Such networks are supposed to have the ability to handle heterogeneous traffic and to manage large span of resources and services effectively. In this paper, a single server G/D/I queuing system with infinite buffer is simulated with the consideration of three input traffic sources: exponential, weibull, and normal distributions. The upper bounds on buffer size are evaluated for the given distributions.http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=92213
From Algorithms To Parallel Architectures: A Formal Approach
No full textIn this paper, we introduce a formal approach for synthesis of parallel architectures. Four different forms are used to express the given algorithms: simultaneous recursion, recursion with respect to different variables, fixed nesting and variable nesting. Four different architectures for the same algorithm are obtained. As an example, a matrix-matrix multiplication algorithm is used to obtain four different optimal architectures. The different architectures of this example are compared in terms of area, time, broadcasting and required hardware. The approach is providing two main features: completeness and correctness.http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=153803&tag=
A Systolic Architecture For Modulo Multiplication
No full textWith the current advances in VLSI technology, traditional algorithms for Residue Number System (RNS) based architectures should be reevaluated to explore the new technology dimensions. In this brief, we introduce A θ(log n) algorithm for large moduli multiplication for RNS based architectures. A systolic array has been designed to perform the modulo multiplication Algorithm. The proposed modulo multiplier is much faster than previously proposed multipliers and more area efficient. The implementation of this multiplier is modular and is based on using simple cells which leads to efficient VLSI realization. A VLSI implementation using 3 micron CMOS technology shows that a pipelined n-bit modulo multiplication scheme can operate with a throughput of 30 M operation per second.http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=475251&tag=
A Production Based System For Formal Verification Of Digital Signal Processing Architectures
No full textIn this paper a new formal hardware verification approach for Digital Signal Processing Architectures based on a production system environment is introduced. The PROVER system (PROduction system for hardware VERification) is implemented using CLIPS (C Language Integrated Production System). A cell library of different hardware components has been implemented. Components in the cell library are described at the transistor level, circuit level, gate level, logical level, and functional level. An example of Carry Select Adder using PROVER is given in the paper.http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=34229
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