66 research outputs found
A new MATLAB/Simulink model of triple-junction solar cell and MPPT based on artificial neural networks for photovoltaic energy systems
No full textAbstractThis paper presents a new Matlab/Simulink model of a PV module and a maximum power point tracking (MPPT) system for high efficiency InGaP/InGaAs/Ge triple-junction solar cell. The proposed technique is based on Artificial Neural Network. The equivalent circuit model of the triple-junction solar cell includes the parameters of each sub-cell. It is also include the effect of the temperature variations on the energy gap of each sub-cell as well as the diode reverse saturation currents. The implementation of a PV model is based on the triple-junction solar cell in the form of masked block in Matlab/Simulink software package that has a user-friendly icon and dialog. It is fast and accurate technique to follow the maximum power point. The simulation results of the proposed MPPT technique are compared with Perturb and Observe MPPT technique. The output power and energy of the proposed technique are higher than that of the Perturb and Observe MPPT technique. The proposed technique increases the output energy per day for a one PV module from 3.37kWh to 3.75kWh, i.e. a percentage of 11.28%
A Low-Power Oscillatory Feature Extraction Unit for Implantable Neural Interfaces
No full textPower and area efficient on-chip feature extraction is needed for future closed-loop neural interfaces. This paper presents a feature extraction unit for neural oscillatory synchrony that bypasses the phase extraction step to reduce hardware complexity. Instead, the sine and cosine of the phase are directly approximated from the real and imaginary components of the signal to calculate the phase-amplitude coupling (PAC) and phase locking value (PLV). The synthesized design achieves state-of-the-art performances at 43 nW/channel and 0.006 mm2, while maintaining sufficient accuracy for seizure detection in epileptic patients.Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Bio-Electronic
Compact Circuit Simulation Model for On-Chip Inductor and Transformer for RF Integrated Circuits
No full textModeling and simulation of floating gate nanocrystal FET devices and circuits
No full textThe nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. ^ Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (ΔVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.
Real study for Photovoltaic system performance in desert environment - Upper Egypt - case study
No full textPulse-position and pulse-amplitude modulation interface for serial data link applications
No full textTime-based recovery technique for pulse-position and pulse-amplitude modulation interface
No full textPower management system for Ethernet-based IoT devices
No full textA novel four switches single inductor differential output synchronous buck converter architecture for the power-over-Ethernet (PoE) system is proposed in this paper. A powered device (PD) interface is designed to meet the PoE IEEE Std 802.3af. The proposed system is designed using 0.18 μm CMOS technology and simulated using SIMUCAD. The simulation results show that the converter has a maximum efficiency of 95% at a switching frequency of 800 kHz. Also, it has a percentage of undershoot and overshoot less than 1% as the load current changes from 0.5 A to 1 A. Using a compensator increases the bandwidth from 61 kHz to 80 kHz and the phase margin increases from 20.7° to 49.96°. To validate the proposed converter architecture and design, a comparison between the proposed work and other reported architectures is provided. It shows that the proposed technique has the highest peak efficiency compared with others. Keywords: Power-over Ethernet, Internet of things, Buck converter, Converter efficiency, MOSFET drive
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