822 research outputs found
Low-frequency noise characterization of strained germanium pMOSFETs
No full textLow-frequency noise in strained Ge epitaxial layers, which are grown on a reverse-graded relaxed SiGe buffer layer, has been evaluated for different front-end processing conditions. It has been shown that the 1/f noise in strong inversion is governed by trapping in the gate oxide (number fluctuations) and not affected by the presence of compressive strain in the channel. However, some impact has been found from the type of halo implantation used, whereby the lowest noise spectral density and the highest hole mobility are obtained by replacing the standard As halo by P implantation. At the same time, omitting the junction anneal results in poor device characteristics, which can be understood by considering the presence of a high density of nonannealed implantation damage in the channel and the gate stack near the source and the drain
A DLTS Perspective on Electrically Active Defects in Plated Crystalline Silicon n<SUP>+</SUP>p Solar Cells
No full textstatus: Publishe
Effects of heavy-ion strikes on fully depleted SOI MOSFETs with ultra-thin gate oxide and different strain-inducing techniques
No full textWe study the immediate and long-term effects of heavy-ion strikes on 65-nm Fully Depleted SOI MOSFETs with different strain engineering solutions. Some of the phenomena already present in bulk devices, such as drain current collapse, are still observed alongside some new long-term effects concerning the degradation kinetics under electrical stress. On the other side, early breakdown seems to vanish. SOI degradation after heavy-ion strikes and during following electrical stress is shown to depend on the strain level and strain-inducing technique. We interpreted these results in terms of radiation-induced defects in the gate and isolation oxide
Experimental Analysis of Trade-Off Between Transistor Efficiency and Unit Gain Frequency of Nanosheet NMOS Transistors
No full textThis work presents a trade-off analysis between transistor efficiency (gm/ID which is proportional to the intrinsic voltage gain Av) and the unit gain frequency (fT) of the nanosheet (NSH) NMOS devices. The analyses were performed experimentally as a function of the inversion coefficient (weak, moderate, or strong inversion levels-IC) in order to determine the best operation region for optimization of both parameters. These analyses were performed with NSH NMOS for the channel length ranging from 28 nm to 200 nm. It was observed that the optimal operation point takes place in the transition between moderate and strong inversion (IC=10), where the highest value obtained for gm/ID x fT was found. In this optimum bias point the AV is 50 dB (L=200 nm) and 37 dB (L=28 nm) and fT is 7 GHz (L=200nm) and 160 GHz (L=28nm), which should be suitable for many applications.University of Sao Paulo LSI/PSI/USPImecSao Paulo State University Unesp, Sao Joao da Boa VistaSao Paulo State University Unesp, Sao Joao da Boa Vist
Electrical and opical characterization of thin semiconductor layers for advanced ULSI devices
No full textDevice Modeling
No full textIn this chapter we describe the modeling approaches developed for the simulation of germanium devices. The main focus will be on metal-insulator-semiconductor (MIS) devices, with particular attention on germanium-on-insulator (GOI) structures. Most of the approaches were originally developed for silicon devices, and thus we will describe them briefly, stressing the differences between Si and Ge and how they translate in different modeling requirements.
The chapter is organized according to a “bottom-up” structure, beginning with Section 9.2 which describes the main differences between the basic properties of Ge and Si, and then spanning from band-structure calculation up to the determination of the drain current in MIS devices for both n-channel and p-channel transistors. However, so far, most of the models have been developed for n-channel devices and cannot be easily extended to p-channel transistors. This is reflected also in the material presented in this chapter, which is more complete and richer of examples for n-channel than it is for p-channel transistors.
Section 9.3 is devoted to band-structure calculation. Since the main interest is in MIS devices, where carriers are quantized in a 2D inversion layer, a relevant fraction of the section is focused on the calculation of the energy states in 2D systems.
In the semi-classical physical framework that we will consider hereafter, the transport modeling is essentially based on the Boltzmann transport equation (BTE), whose general solution is
very complex because the scattering integrals make the stationary BTE an integral–differential equation in a multi-dimensional space of the phases (which has six dimensions for a bulk semiconductor and four dimensions for a 2D inversion layer). A dramatic simplification is
obtained by neglecting the scattering term, which leads to the ballistic transport regime. This simplified approach is mostly useful to investigate the upper-limits of the performance that can be attained with a device structure, so that it can be used for a preliminary investigation of the possible benefits related to new device structures, such as Ge channel Metal-oxidesemiconductor
field effect transistor (MOSFETs). This aspect is described in Section 9.4, where comparisons between Si and Ge devices are provided.
The solution of the BTE beyond the ballistic approximation is considered in Section 9.5, starting from approximate solutions such as the Drift-Diffusion approach, and then considering more accurate approaches, such as the Monte-Carlo (MC) method.
Finally, in Section 9.6 we will draw our conclusion and propose a “roadmap” for the forthcoming activities in the field of the simulation of advanced Ge devices
Low-frequency noise behavior of SiO2-HfO2 dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness
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