40 research outputs found
Design and implementation of a belief-propagation scheduler for multicast traffic in input-queued switches
Get PDFScheduling multicast traffic in input-queued switches to maximize throughput requires solving a hard combinatorial optimization problem in a very short time. This task advocates the design of algorithms that are simple to implement and efficient in terms of performance. We propose a new scheduling algorithm, based on message passing and inspired by the belief propagation paradigm, meant to approximate the provably-optimal scheduling policy for multicast traffic. We design and implement both a software and a hardware version of the algorithm, the latter running on a NetFPGA. We compare the performance and the power consumption of the two versions when integrated in a software router. Our main findings are that our algorithm outperforms other centralized greedy scheduling policies, achieving a better tradeoff between complexity and performance, and it is amenable to practical high-performance implementations
On emulating hardware/software co-designed control algorithms for packet switches
No full textHardware accelerators in networking systems for control algorithms offer a promising approach to scale performance. To that end, several research efforts have been devoted to verify a hardware version of complex control algorithms but only for small-scale hardware unit tests. In this paper we propose and evaluate an emulation framework, in which such control algorithm accelerators can be integrated to design a packet switch, able both to forward real traffic and to enable extensive experimental evaluation and demonstration scenarios. As a case study, we have integrated in the proposed framework a Belief-Propagation-driven algorithm accelerator for multicast packet scheduling. Copyright © 2014 ICST
Experiences and challenges in building next-gen optically disaggregated datacenters : (Invited Paper)
No full texton SoC platforms
No full textSystem- and application-level support for runtime hardware reconfiguratio
Extracting coarse-grained pipelined parallelism out of sequential applications for parallel processor arrays
No full textWe present development and runtime support for building application specific data processing pipelines out of sequential code, and for executing them on a general purpose platform that features a reconfigurable Parallel Processor Array (PPA). Our approach is to let the programmer annotate the source of the application to indicate the desired pipeline stages and associated data flow, with little code restructuring. A pre-processor is then used to transform the annotated program into different code segments according to the indicated pipeline structure, generate the corresponding executable code, and produce a bundled application package containing all executables and deployment information for the target platform. There are special mechanisms for setting up the application-specific pipeline structure on the PPA and achieving integrated execution in the context of a general-purpose operating system, enabling the pipelined application to access the usual system peripherals and run concurrently with other conventional programs. To verify our approach, we have built a prototype system using soft processor arrays on an embedded FPGA platform, and transformed a well-known application into a pipelined version that executes successfully on our prototype. © 2009 Springer Berlin Heidelberg
Supporting multitasking of pipelined computations on embedded parallel processor arrays
No full textThis paper presents software support that enables seamless task restructuring and load balancing of pipelined applications at runtime, making it possible to dynamically pick the stages that will be executed as separate tasks on distinct CPUs, depending on the currently available resources and the execution context. This functionality is integrated in a development and execution framework for pipelined applications targeted at reconfigurable (in terms of interconnections), heterogeneous (in terms of architecture and/or clock speed), distributed memory, embedded Parallel Processor Arrays (PPAs). The primary motivation for this work is to support the use of PPA on-chip architectures, which are currently considered as dedicated accelerators, in a multitasking execution context where the available processor cores are distributed among concurrently executing applications. As a proof-of-concept, we discuss the execution of two pipelined applications on an FPGA-based prototype platform that features Xilinx Microblaze soft processor arrays. © 2009 IEEE
Physics-inspired methods for networking and communications
Get PDFAdvances in statistical physics relating to our understanding of large-scale complex systems have recently been successfully applied in the context of communication networks. Statistical mechanics methods can be used to decompose global system behavior into simple local interactions. Thus, large-scale problems can be solved or approximated in a distributed manner with iterative lightweight local messaging. This survey discusses how statistical physics methodology can provide efficient solutions to hard network problems that are intractable by classical methods. We highlight three typical examples in the realm of networking and communications. In each case we show how a fundamental idea of statistical physics helps solve the problem in an efficient manner. In particular, we discuss how to perform multicast scheduling with message passing methods, how to improve coding using the crystallization process, and how to compute optimal routing by representing routes as interacting polymers
VirtueMAN: A software-defined network architecture for WiFi-based metropolitan applications
No full text
