68 research outputs found
Modelering en mitigatie van parametrische tijds-afhankelijke variabiliteit in digitale systemen
No full textCurrent and future semiconductor technology nodes, bring about a variety of challenges that pertain to the reliability and dependability of digital integrated systems. Compounds, such as high-κ materials in the transistor gate stack, tend to intensify the time-zero and time-dependent variability of transistors. A case, can certainly be made for the phenomena like Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN). The use of such modern materials is also coupled to an aggressive downscaling trend, which further amplifies matter discretization within the transistor's channel. These are two major manufacturing trends that give rise to time-dependent variability in integrated digital systems. It stands to reason, that as the materials become more variable, the error rates experienced at the circuit- or even system-level are also intensified. Coupled to increasing integrated circuit functionality (namely, the `"More than Moore" trend), it is reasonable to expect that future digital chips will be exhibiting reliability profiles that vary across the chip's lifetime.
The goal of the research presented in the current text is to study the above observations both regarding the modeling and the mitigation of time-dependent variability. Target systems, naturally, constitute digital integrated circuits, such as processors and memories thereof. The current research contributes with specific reductions to practice that aim to confirm existing techniques and develop novel insight into the modeling and mitigation of time-dependent variability. As such, the current text is broadly split into two major parts.
The modeling part starts with the reiteration of atomistic modeling concepts, which are very useful in the analysis of phenomena like BTI and RTN, especially for deca-nanometer transistors. As a result, the complexity of atomistic models for integrated circuit aging analysis is made abundantly clear. In order to alleviate the complexity of circuit reliability analysis across the system lifetime, the current research has formulated the concept of the Compact Digital Waveform (CDW). This format targets regions of circuit operation that are similar from a waveform point of view (e.g. similar frequency or duty cycle) and abstracts them to a single point. This enables striding over circuit lifetime intervals, while retaining key features of atomistic reliability models (e.g. workload dependency).
Still on the modeling front, the current research additionally contributes towards exposing transistor variability information to the architecture level. The metric of choice in this case is the component failure probability (Pfail). This is typically required by system designers to appropriately provision their systems with appropriate disabling or correction mechanisms. In order to derive the Pfail, this text features the Most Probable Failure Point (MPFP) method, which is applied for the cases of BTI/RTN variability. Two modeling approaches are used for these aging phenomena and observations are drawn regarding the importance of accurate standard deviation capturing (regarding the threshold voltage variability). A statistical reformulation of the MPFP concept is also presented towards handling standard cells, apart from memory components.
The failure of system components has traditionally been triggering some sort of reaction from the system, at least as far as detectable errors are concerned. Academia and industry have been using the term Reliability, Availability and Serviceability (RAS) in order to refer to such techniques. Their invocation is strictly coupled to the rate of errors that appears at the circuit level and typically comes at a measurable performance cost.
On the mitigation side, the starting point of the current research is a simple, rollback-based RAS technique that aims to recover a system from transient errors. This concept has been implemented on a research-grade many-core platform, in the data plane of which errors are injected at a user-defined rate. The rollbacks make sure the running application is brought to an earlier correct state, so that execution can continue. This fail/stop model, however granular, is creating a measurable drawback in the timely execution of the running application. It is reasonable to explore that a portion of injected errors may not corrected in order to reduce this performance overhead. In view of this trade-off, the current work explores the trade-off between application correctness, performance and energy budget, in search of the optimal operation points.
The final milestone of the current work is a generally applicable solution for the problem of dependable performance, in view of temporal RAS overheads such as the one illustrated above. Towards that direction, the issue of dependable performance is formulated from scratch and a control-theoretic solution is proposed. More specifically, a PID controller is used in order to manipulate the frequency of a processor, within which RAS schemes are invoked at the price of additional clock cycles. The concept is verified within the current research, both with simple simulations and on a real processing platform.status: Publishe
Fast Estimations of Failure Probability Over Long Time Spans
No full textShrinking of device dimensions has undoubtedly enabled the very large scale integration of transistors on electronic chips. However, it has also brought to surface time-zero and time-dependent variation phenomena that degrade system's performance and threaten functional operation. Hence, the need to capture and describe these mechanisms, as well as effectively model their impact is crucial. To this extent, we follow existing models and propose a complete framework that evaluates failure probability of electronic components. To assess our framework, a case-study of packet-switched Network on Chip (NoC) routers is presented, studying the failure probability of its SRAM buffers
Enhanced Cellular Materials through Multiscale, Variable-Section Inner Designs: Mechanical Attributes and Neural Network Modeling
No full textIn the current work, the mechanical response of multiscale cellular materials with hollow variable-section inner elements is analyzed, combining experimental, numerical and machine learning techniques. At first, the effect of multiscale designs on the macroscale material attributes is quantified as a function of their inner structure. To that scope, analytical, closed-form expressions for the axial and bending inner element-scale stiffness are elaborated. The multiscale metamaterial performance is numerically probed for variable-section, multiscale honeycomb, square and re-entrant star-shaped lattice architectures. It is observed that a substantial normal, bulk and shear specific stiffness increase can be achieved, which differs depending on the upper-scale lattice pattern. Subsequently, extended mechanical datasets are created for the training of machine learning models of the metamaterial performance. Thereupon, neural network (NN) architectures and modeling parameters that can robustly capture the multiscale material response are identified. It is demonstrated that rather low-numerical-cost NN models can assess the complete set of elastic properties with substantial accuracy, providing a direct link between the underlying design parameters and the macroscale metamaterial performance. Moreover, inverse, multi-objective engineering tasks become feasible. It is shown that unified machine-learning-based representation allows for the inverse identification of the inner multiscale structural topology and base material parameters that optimally meet multiple macroscale performance objectives, coupling the NN metamaterial models with genetic algorithm-based optimization schemes
Μοντελοποίηση και αντιμετώπιση παραμετρικής χρονικά εξαρτημένης μεταβλητότητας ψηφιακών συστημάτων
No full textCurrent and future semiconductor technology nodes, bring about a variety of challenges that pertain to the reliability and dependability of digital integrated systems. Compounds, such as high-κ materials in the transistor gate stack, tend to intensify the time-zero and time-dependent variability of transistors. A case, can certainly be made for the phenomena like Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN). The use of such modern materials is also coupled to an aggressive downscaling trend, which further amplifies matter discretization within the transistor's channel. These are two major manufacturing trends that give rise to time-dependent variability in integrated digital systems. It stands to reason, that as the materials become more variable, the error rates experienced at the circuit- or even system-level are also intensified. Coupled to increasing integrated circuit functionality (namely, the "More than Moore" trend), it is reasonable to expect that future digital chips will be exhibiting reliability profiles that vary across the chip's lifetime. The goal of the research presented in the current text is to study the above observations both regarding the modeling and the mitigation of time-dependent variability. Target systems, naturally, constitute digital integrated circuits, such as processors and memories thereof. The current research contributes with specific reductions to practice that aim to confirm existing techniques and develop novel insight into the modeling and mitigation of time-dependent variability. As such, the current text is broadly split into two major parts.The modeling part starts with the reiteration of atomistic modeling concepts, which are very useful in the analysis of phenomena like BTI and RTN, especially for deca-nanometer transistors. As a result, the complexity of atomistic models for integrated circuit aging analysis is made abundantly clear. In order to alleviate the complexity of circuit reliability analysis across the system lifetime, the current research has formulated the concept of the Compact Digital Waveform (CDW). This format targets regions of circuit operation that are similar from a waveform point of view (e.g. similar frequency or duty cycle) and abstracts them to a single point. This enables striding over circuit lifetime intervals, while retaining key features of atomistic reliability models (e.g. workload dependency).Still on the modeling front, the current research additionally contributes towards exposing transistor variability information to the architecture level. The metric of choice in this case is the component failure probability (Pfail). This is typically required by system designers to appropriately provision their systems with appropriate disabling or correction mechanisms. In order to derive the Pfail, this text features the Most Probable Failure Point (MPFP) method, which is applied for the cases of BTI/RTN variability. Two modeling approaches are used for these aging phenomena and observations are drawn regarding the importance of accurate standard deviation capturing (regarding the threshold voltage variability). A statistical reformulation of the MPFP concept is also presented towards handling standard cells, apart from memory components.The failure of system components has traditionally been triggering some sort of reaction from the system, at least as far as detectable errors are concerned. Academia and industry have been using the term Reliability, Availability and Serviceability (RAS) in order to refer to such techniques. Their invocation is strictly coupled to the rate of errors that appears at the circuit level and typically comes at a measurable performance cost.On the mitigation side, the starting point of the current research is a simple, rollback-based RAS technique that aims to recover a system from transient errors. This concept has been implemented on a research-grade many-core platform, in the data plane of which errors are injected at a user-defined rate. The rollbacks make sure the running application is brought to an earlier correct state, so that execution can continue. This fail/stop model, however granular, is creating a measurable drawback in the timely execution of the running application. It is reasonable to explore that a portion of injected errors may not corrected in order to reduce this performance overhead. In view of this trade-off, the current work explores the trade-off between application correctness, performance and energy budget, in search of the optimal operation points.The final milestone of the current work is a generally applicable solution for the problem of dependable performance, in view of temporal RAS overheads such as the one illustrated above. Towards that direction, the issue of dependable performance is formulated from scratch and a control-theoretic solution is proposed. More specifically, a PID controller is used in order to manipulate the frequency of a processor, within which RAS schemes are invoked at the price of additional clock cycles. The concept is verified within the current research, both with simple simulations and on a real processing platform.Οι σύγχρονες τεχνολογιές πυριτίου φέρνουν στο προσκήνιο μία ποικιλία προκλήσεων για την αξιοπιστία ψηφιακών ολοκληρωμένων κυκλωμάτων. Δομικά στοιχεία, όπως τα υλικά υψηλής διηλεκτρικής σταθεράς στην πύλη των τρανζίστορ, παρουσιάζουν στατική αλλά και χρονικά εξαρτόμενη μεταβλητότητα. Αντιπροσωπευτικό παράδειγμα είναι τα φαινόμενα Bias Temperature Instability (BTI) και Random Telegraph Noise (RTN). Η χρήση τέτοιων υλικών υψηλής τεχνολογίας επιτρέπει την σμήκρυνση των ολοκληρωμένων κυκλωμάτων, η οποία επιπρόσθετα ενισχύει την διακριτοποίηση της ύλης μέσα στο κανάλι των τρανζίστορ. Αυτές οι κατασκευαστικές τάσεις προάγουν την στατική και χρονικά εξαρτόμενη μεταβλητότητα των ψηφιακών ολοκληρωμένων κυκλωμάτων. Είναι λογικό ότι όσο ενισχύεται η μεταβλητότητα των υλικών, τόσο πληθαίνουν τα σφάλματα σε επίπεδο κυκλώματος και συστήματος. Σε συνδυασμό με τις συνεχώς διευρυνόμενες λειτουργίες ολοκληρωμένων κυκλωμάτων (τάση "More than Moore"), είναι λογικό να αναμένουμε ότι μελλοντικά ολοκληρωμένα κυκλώματα θα παρουσιάζουν αξιοπιστία που μεταβάλεται κατά τη διάρκεια της "ζωής" τους. Ο στόχος της παρούσας έρευνας είναι να μοντελοποίησει αλλά και να αναπτύξει τρόπους αντιμετώπισης της στατικής και χρονικά εξαρτόμενης μεταβλητότητας. Στοχευόμενα συστήματα είναι τα ψηφιακά ολοκληρωμένα συστήματα, όπως επεξεργαστές και μνήμες αυτών. Η παρούσα έρευνα παρουσιάζει πρακτικές εφαρμογές που επιβεβαιώνουν και επεκτείνουν τεχνικές για την μοντελοποίηση και αντιμετώπιση της στατικής και χρονικά εξαρτόμενης μεταβλητότητας ολοκληρωμένων συστημάτων. Το παρόν κείμενο είναι διαχωρισμένο σε δύο κύρια μέρη.Το πρώτο μέρος αφορά τη μοντελοποίηση και ξεκινά με μία επανάληψη βασικών εννοιών ατομιστικής προσομοίωσης, που χρησιμοποιείται εκτεταμένα για φαινόμενα όπως BTI και RTN, ειδικά για τρανζίστορ σε διαστάσεις δεκάδων νανομέτρων. Κατά συνέπεια, εκτίθεται η πολυπλοκότητα αυτών των μοντέλων. Η παρούσα έρευνα αντιμετωπίζει την υψηλή πολυπλοκότητα της μοντελοποίησης αξιοπιστίας προτείνοντας την έννοια της συμπαγούς ψηφιακής κυματομορφής (Compact Digital Waveform - CDW). Αυτό το πρότυπο απεικόνισης κυματομορφών απομονώνει διαδοχικές περιοχές ενός σήματος με παρόμοια μορφή (π.χ. βάσει συχνότητας) και τις συνοψίζει σε ένα σημείο. Αυτό επιτρέπει στην προσομοίωση να υπερπηδά διαστήματα ζωής του κυκλώματος, ενώ διατηρούνται τα χαρακτηριστικά του σήματος τα οποία είναι αναγκαία για την ορθότητα του ατομιστικού μοντέλου. Παραμένοντας στο μέτωπο της μοντελοποίησης, η παρούσα έρευνα συνεισφέρει επιπρόσθετα στην έκθεση της μεταβλητότητας των τρανζίστορ στο επίπεδο αρχιτεκτονικής. Η μετρική που επιλέγεται είναι η πιθανότητα αποτυχίας του εκάστοτε υποσυστήματος, Pfail. Τέτοιες μετρικές είναι απαραίτητες στους αρχιτέκτονες υπολογιστών, ώστε να μπορούν να λάβουν κατάλληλα σχεδιαστικά μέτρα απενεργοποίησης ή διόρθωσης σφαλμάτων. Για τον υπολογισμό του Pfail χρησιμοποιείται η τεχνική Most Probable Failure Point (MPFP), η οποία εφαρμόζεται στο παρόν κείμενο για την περίπτωση μεταβλητότητας λόγω BTI/RTN. Επίσης, αποδεικνύεται η σημασία του σωστού υπολογισμού τυπικής απόκλισης της μεταβολής τάσης κατωφλίου για τον υπολογισμού του Pfail.Η αποτυχία ορισμένων υποσυστημάτων σε ένα ολοκληρωμένο κύκλωμα συνήθως προκαλεί κάποια αντίδραση από εσωτερικούς μηχανισμούς. Ο όρος Αξιοπιστία, Διαθεσιμότητα και Επισκευασιμότητα (Reliability, Availability and Serviceability - RAS) χρησιμοποιείται στη βιομηχανία και ακαδημία για να περιγράψει τέτοιες τεχνικές. Η χρήση τέτοιων τεχνικών αντιμετώπισης συνδέεται άρρικτα με τον ρυθμό εμφάνισης σφαλμάτω σε κυκλωματικό επίπεδο.Το δεύτερο μέρος της παρούσας έρευνας αφορά την αντιμετώπιση της χρονικά εξαρτόμενης μεταβλητότητας. Σημείο έναρξης είναι μία απλή RAS τεχνική που χρησιμοποιείται για την αντιμετώπιση παροδικών σφαλμάτων στο υλικό και βασίζεται σε επαναφορά εκτέλεσης. Η τεχνική αυτή υλοποείται σε μία ερευνητική πλατφόρμα πολλών πυρήνων. Οι επαναφορές εκτέλεσης εγγυόνται ότι η εκτέλεση της εφαρμογής επανέρχεται σε σωστή αρχιτεκτονική κατάσταση. Ωστόσο, αυτό το μοντέλο διακοπής/εκτέλεσης, όσο λεπτομερείς και να είναι οι επαναφορές, επιβαρύνει την επίδοση της εκτέλεσης προσθέτοντας ένα χρονικό κόστος. Είναι ιδιαίτερα ενδιαφέρον να διερευνήσουμε κατά πόσο ένα υποσύνολο των σφαλμάτων μπορεί να αγνοηθεί, με σκοπό να μειώσουμε την χρονική επίδραση των επαναφορών εκτέλεσης. Στην παρούσα έρευνα, παρουσιάζουμε αναλυτικά τον συμβιβασμό μεταξύ της ορθότητας εκτέλεσης, της επίδοσης και της καταναλυσκόμενης ενέργειας. Επιπρόσθετα, η παρούσα έρευνα προτείνει τη γενίκευση του προβλήματος αξιόπιστης επίδοσης ψηφιακών συστημάτων, ειδικότερα υπό την επίδραση τεχνικών RAS. Σε αυτή τη κατεύθυνση, παρουσιάζεται η μαθηματική θεμελίωση του προβλήματος της αξιόπιστης επίδοσης και προτείνεται μία τεχνική αυτομάτου ελέγχου για την αντιμετώπισης της. Ποιο συγκεκριμένα, ένας ελεγκτής PID χρησιμοποείται για να διαμορφώσει την συχνότητα ενός επεξεργαστή κατά τη διάρκεια της εκτέλεσης. Η αποτελεσματικότητα αυτής της τεχνικής παρουσιάζεται τόσο μέσα από προσομοιώσεις όσο και μέσα από υλοποίηση λογισμικού που εκτελείται σε πραγματική πλατφόρμα
Conjugate Dynamic Programming
No full textIn decision making problems, the ability to compute the optimal solution can pose a serious challenge. Dynamic Programming (DP) aims to provide a framework to deal with a category of such problems, namely ones that involve sequential decision making. By dividing the original control problem into sub-problems and solving it backwards in time, from the end of the time horizon to the start, the method can compute a map of optimal solutions with respect to the initial condition. In order to divide the original problem into subproblems the DP method takes advantage of the principle of optimality, which states that a sub-solution of the optimal solution should be the optimal solution for the equivalent subproblem. In control systems, where the state and decision spaces are continuous, the original DP framework can be intractable due to the size of the discretization needed to simulate the continuous space. Therefore, efficient approximations are needed to solve such problems. One promising method is called Conjugate Dynamic Programming (CDP). The CDP algorithm is able to transform the original framework and solve problems in the conjugate domain providing a computational advantage over the standard method. In this work, we aim to improve and extend the setting under which the CDP algorithm operates, thus providing a more concrete advantage over standard method . In that regard, we will extract the optimal control actions from within the CDP algorithm, eliminating the need for solving an extra optimization problem for their computation. In addition, we will introduce a different interpolation technique that can outperform the current one, in certain scenarios, thus granting the user more choice when solving a decision making problem.Mechanical Engineering | Systems and Contro
Strength, ductility and cyclic loading performance of plant and animal-based, natural fiber structures
No full textThe current contribution investigates the mechanics of helically-braided, load-bearing structures crafted from plant and animal-based natural materials, including goat hair, coconut, palm, manila (abaca) fibers, and palm leaves. The constituent fibers are subjected to chemical analysis through spectroscopy, while geometric and material density attributes are assessed. Their static and cyclic mechanical attributes are analyzed, identifying primal differences among the fiber types for each loading type case. Manila fiber-based structures yield the highest effective static properties, with peak stress values above 70 MPa and energy absorptions up to 30 J∕mm3, followed by coconut-fiber structures with corresponding values of 33 MPa and 7.3 J∕mm3. These values are approximately an order of magnitude higher that those recorded for animal-fiber-based, helically-braided structures. The associated cyclic loading characteristics differ significantly from the corresponding static properties. Moderate static strength coconut fiber structures exhibit substantially higher hysteresis loss values (above 0.04 J∕MPa after several loading cycles) in comparison to the stiffer, manila-based designs. Furthermore, the ratio of the hysteretic loss energy to the total energy differs, with low-strength palm leaf fiber structures to yield a comparable performance with the high static strength, manila-fiber designs. In all cases, the evolution of the hysteretic energy loss magnitude as a function of the loading cycle is characterized, deriving correlations among the structural composition and the recorded cyclic response performance. Moreover, Ashby-type classifications are conducted with respect to a wide range of natural materials, highlighting the distinctive energy absorption capacity of manila and coconut fiber designs, approaching 1000 kJ∕kg, values that are several times higher than those recorded for metallic helically-braided structures
Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations
No full textUnderstanding timing impact of BTI/RTN with massively threaded atomistic transient sumulations
No full text- …
