1,720,966 research outputs found
Characterization and TCAD Simulation of the Electrostatic Potential Distortion in HV-ICs due to Losses in the Epoxy Mold Compound
No full textThe presence of space charge and leakage current within the epoxy-based mold compound (EMC) used as encapsulation material for high-voltage integrated circuits (HV-ICs) can significantly impact long-term reliability and performance of the devices when finally packaged. Moreover, the role of moisture, even if very little absorbed by the EMCs, can lead to a strong increase of the EMC conductivity, resulting in a larger electrostatic potential distortion when compared with the case of a perfectly dry insulating package. To directly measure the effects induced by space charge accumulation in dry and wet conditions, a dedicated test chip integrating a charge-sensor array has been manufactured and characterized. From the measured currents, the value of the electrostatic potential at the EMC/passivation interface has been accurately extracted. Moreover, the charge-sensor currents have been monitored during the discharging transient to investigate the concurrent coupling effects of the inner wiring and bondpads in discharge conditions
Characterization and TCAD Modeling of the Lateral Space Charge Accumulation in Epoxy Molding Compound in Packaged HV-ICs
Full text linkThe reliability of high-voltage (HV) integrated circuits (ICs) can be significantly affected by space charge accumulation at the interface between the passivation layer and the epoxy molding compound (EMC) which acts as encapsulation material. The incorporation of moisture, which significantly increases the EMC conductivity, can lead to a stronger distortion of the electric field with a consequent breakdown instability. Moreover, the distance of the integrated-circuit active regions from the peripheral bond pads and wire would require a thorough optimization. To investigate the role played by the EMC under such conditions, a dedicated test chip made by an array of charge sensors covering short distances from bon-pads has been manufactured. A novel technique has been used to estimate the amount of space charge in the EMC independent of the bias applied to the bond pads. The outcome of the experiments has been explained by performing 2-D TCAD simulations of the structure under investigation which accurately account for the charge transport mechanisms of the EMC
Understanding the impact of split-gate LDMOS transistors: Analysis of performance and hot-carrier-induced degradation
Full text linkIn this paper a split-gate LDMOS transistor is investigated. A dedicated terminal, namely split-gate, is introduced in order to control the field plate region separately with respect to the channel region. The performances of the device, in terms of on-resistance, breakdown voltage and capacitances, are compared with those of a conven-tional device. The hot-carrier-induced degradation of the device is also investigated, highlighting the influence of the split-gate voltage. This work allows identifying a tradeoff between the performance and reliability of the component, which is controlled by the voltage applied to the split-gate terminal
Characterization and numerical analysis of breakdown in thick amorphous SiO2 capacitors
Full text linkCharge transport in thick amorphous silicon dioxide capacitors for integrated galvanic insulators is experimentally investigated and analyzed through numerical simulations carried out with a commercial TCAD tool. The material intrinsic defectivity and the large biases applied to such devices give rise to a leakage current which is responsible for degradation and failure. Hence it is crucial to have a complete understanding of the charge-transport main physical mechanisms in amorphous silicon oxide. In particular, charge injection at contacts and charge build-up due to trapping/de-trapping mechanisms in the bulk of the oxide are expected to play a crucial role and their complex coupled interaction needs to be investigated via a TCAD-based approach. For this reason, time-dependent dielectric breakdown measurements at constant-current stresses and voltage-ramp stresses up to breakdown have been performed on thick metal-insulator–metal structures, and numerical simulations have been carried out so to predict the failure mechanisms. To this purpose, special attention has been devoted to the physical modeling of defects and impact-ionization generation
Constant-current time dependent dielectric breakdown in thick amorphous SiO2 capacitors
No full textCharge transport in thick amorphous silicon dioxide capacitors for integrated galvanic insulators is experimentally investigated and analyzed through numerical simulations carried out with a commercial TCAD tool. The material intrinsic defectivity and the large biases applied to such devices give rise to a leakage current which is responsible of degradation and failure. Hence it is crucial to have a complete understanding of the charge-transport main physical mechanisms in amorphous silicon oxide. For this reason, constant-current time dependent dielectric breakdown measurements have been performed on thick metal-insulator-metal structures and, in order to gain insight on the role of defects on breakdown, numerical simulations have been compared to experiments
Anomalous increase of leakage current in epoxy moulding compounds under wet conditions
Full text linkAn interdigitated capacitor embedded in the EMC has been realized and characterized under controlled humidity conditions by applying a DC step voltage and monitoring the leakage current as a function of time. Both experimental characterization and TCAD simulations of dry and wet EMC samples have been carried out to fully understand the involved charge transport mechanisms. The anomalous increase of current with time in wet conditions is explained assuming a build-up of space charge directly induced by the high-injection at the metal electrodes. The assumption is confirmed by TCAD simulations
Full Understanding of Hot Electrons and Hot/Cold Holes in the Degradation of p-channel Power LDMOS Transistors
Full text linkDegradation induced by hot-carrier stress is a crucial issue for the reliability of power LDMOS transistors. This is even more true for the p-channel LDMOS in which, unlike the n-channel counterpart, both the majority and minority carriers play a fundamental role on the device reliability. An in-depth study of the microscopic mechanisms induced by hot-carrier stress in new generation BCD integrated p-channel LDMOS is presented in this paper. The effect of the competing electron and hole trapping mechanisms on the on-resistance drift has been thoroughly analyzed. To this purpose, TCAD simulations including the deterministic solution of Boltzmann transport equation and the microscopic degradation mechanisms have been used, to the best of our knowledge, for the first time. The insight gained into the degradation sources and dynamics will provide a relevant basis for future device optimization
Novel TCAD Approach for the Investigation of Charge Transport in Thick Amorphous SiO2 Insulators
Full text linkA TCAD approach for the investigation of charge transport in thick amorphous silicon dioxide is presented for the first time. Thick oxides are investigated representing the best candidates for integrated galvanic insulators in future power applications. The large electric fields, such devices experience and the preexisting defects in the amorphous material, give rise to a leakage current, which leads to degradation and failure. Hence, it is crucial to have a complete understanding of the main physical mechanisms responsible for the charge transport in amorphous silicon oxide. For this reason, metal-insulator-metal structures have been experimentally characterized at different high-field stress conditions and a TCAD approach has been implemented in order to gain insight into the microscopic physical mechanisms responsible for the leakage current. In particular, the role of charge injection at contacts and charge build-up due to trapping-detrapping mechanisms in the bulk of the oxide layer has been investigated and modeled to the purpose of understanding the oxide behavior under dc- and ac-stress conditions. Numerical simulations have been compared against experiments to quantitatively validate the proposed approach
Thickness-dependent dielectric breakdown in thick amorphous SiO2 capacitors
Full text linkHigh-voltage dielectric breakdown of thick amorphous silicon dioxide capacitors for galvanic insulation is experimentally investigated and analyzed through numerical simulations carried out with a commercial TCAD tool. Silicon oxide metal-insulator–metal capacitors are used as back-end inter-level dielectric layers in integrated circuits. The large biases such devices must sustain and the material intrinsic defectivity give rise to a leakage current which is responsible of degradation and failure. Therefore, the understanding of the degradation mechanisms of the insulator is an essential prerequisite for its safe operation. For this reason, high-voltage dielectric breakdown measurements have been performed under DC-stress conditions on thick metal-insulator–metal structures with different oxide thickness and, in order to gain insight on the role of defects on breakdown, numerical simulations have been compared to experiments
Understanding the impact of split-gate LDMOS transistors: Analysis of performance and hot-carrier-induced degradation
Full text linkIn this paper a split-gate LDMOS transistor is investigated. A dedicated terminal, namely split-gate, is introduced in order to control the field plate region separately with respect to the channel region. The performances of the device, in terms of on-resistance, breakdown voltage and capacitances, are compared with those of a conventional device. The hot-carrier-induced degradation of the device is also investigated, highlighting the influence of the split-gate voltage. This work allows identifying a tradeoff between the performance and reliability of the component, which is controlled by the voltage applied to the split-gate terminal
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