11 research outputs found
Electrical Stability of MOS Structures With AlON and Al2O3 Dielectrics Deposited on n-and p-Type GaN
No full textThis article discusses the electrical stability of MOS structures on n-and p-type GaN for two different dielectrics, AlON and Al2O3, deposited by atomic layer deposition (ALD). Threshold voltage hysteresis was evaluated by means of capacitance-voltage (C-V ) double sweep measurements, performed on MOS capacitors. MOS structures on p-doped GaN show up to two orders of magnitude higher effective trapped charge density than on n-GaN. Moreover, AlON results in 10 times less trapped charge than Al 2 O 3 on p-GaN. The leakage current is also identified as an important factor in defining the electrical stability at high electric fields, due to the enhanced injection of electrons into the MOS stack. Electron trapping is shown to happen either at the dielectric-semiconductor interface or in border traps. AlON results in lower flat-band and threshold voltages likely due to the resulting fixed interface charge from surface reconstruction. The effect of the n-type doping density as well as of dry etch damage on the effective trapped charge after injection has been shown to be minimal. These results are important for different insulated gate device architectures. We show that extremely low threshold voltage hysteresis values can be reached in a trench-shaped gate GaN MOSFET using AlON as an interface dielectric
Demonstration of High-quality GaN Epitaxy on 200 mm Engineered Substrates for Vertical Power Device Fabrication
No full textReliability of p-GaN gate HEMTs in reverse conduction
No full textSynchronousbuck converter comprises a low side (LS) and a high side (HS) switch, where the HS switch works in the first quadrant (forward conduction) whereas the LS switch works in the third quadrant (reverse conduction). However, the reliability of the p-GaN gate high electron mobility transistor (HEMT) in reverse conduction is unclear. In this work, a comprehensive evaluation of this conduction mode for 200-V HEMTs was conducted. First, devices were subjected to time-dependent breakdown (TDB) measurements. By comparing different device configurations, the time to failure (TTF) was found to only scalewith the number of gate fingers instead of the gate width W-G, proving the critical spots are the intersection of gate fingers over the N implantation isolation. The reverse operation voltage of V-DS for ten years lifetime was extrapolated to be -5.4 V, corresponding to a failure of 0.01% and 100 gate fingers. Second, the devices were submitted to 200-V V-DS OFF-state stress for 10 s, after which the reverse drain current saw a negligible degradation. Third, the reverse conduction of the HEMTs only showed a very limited deterioration after a long-time bias temperature instability (BTI) stress at V-DS = -5.5 V and V-GS = 0 V. This work proves the p-GaN gate HEMTs bear a high reliability in reverse conduction, which can simplify the design of synchronous power system
Development and analysis of thick GaN drift layers on 200 mm CTE-matched substrate for vertical device processing
No full textAbstract This work reports the epitaxial growth of 8.5 µm-thick GaN layers on 200 mm engineered substrates with a polycrystalline AlN core (QST by QROMIS) for CMOS compatible processing of vertical GaN power devices. The epitaxial stack contains a 5 \upmu μ m thick drift layers with a Si doping density of 2 × 1016 cm−3 and total threading dislocation density of 4 × 108 cm−2. The thick drift layer requires fine-tuning of the epitaxial growth conditions to keep wafer bow under control and to avoid the formation of surface defects. Diode test structures processed with this epitaxial stack achieved hard breakdown voltages > 750 V, which is shown to be limited by impurity or metal diffusion from the contact metal stack into threading dislocations. Conductive Atomic Force Microscopy (cAFM) reveals some leakage contribution from mixed type dislocations, which have their core structure identified as the double 5/6 atom configuration by scanning transmission electron microscopy images. Modelling of the leakage conduction mechanism with one-dimensional hopping conduction shows good agreement with the experimental data, and the resulting fitting parameters are compared to similar findings on silicon substrates. The outcome of this work is important to understand the possibilities and limitations of vertical GaN devices fabricated on large diameter wafers
AlON gate dielectric and gate trench cleaning for improved relia-bility of vertical GaN MOSFET
No full textDevice optimization for 200V GaN-on-SOI platform for monolithicly integrated power circuits
No full textThe device performance of monolithically integrated power Schottky barrier diodes (SBDs) and depletion-mode (D-mode) MIS HEMTs is studied in relation to the thickness of the gate dielectric, the gate-edge termination (GET) layer and AlGaN barrier. Special attention is paid to the turn-on voltage (V-TON), ON-resistance (R-ON), device dispersion, leakage current and breakdown voltage (V-BD) of SBDs and D-mode MIS-HEMTs. Based on the current design, SBDs show the lowest dynamic RON for devices with 7.5-9.5 nm AlGaN barrier thickness and 25-35 nm GET thicknesses. The best performance of the D-mode MIS-HEMTs is observed for devices with 5.5 nm AlGaN barrier thickness and 45 nm gate dielectric thickness
1.2 kV Enhancement-Mode p-GaN Gate HEMTs on 200 mm Engineered Substrates
No full textNo Statement Availabl
AUTHOR REPLY TO: Mean platelet volume in pseudoexfoliation syndrome and glaucoma
No full text[Abstract Not Available
200 V GaN-on-SOI Smart Power Platform for Monolithic GaN Power ICs
No full textThis paper demonstrates a 200 V GaN-on-SOI smart power integrated circuits (ICs) platform developped on 200 mm substrates. Depletion-mode (d-mode) MIS-HEMTs and Gated-Edge-Termination Schottky barrier diodes (GET-SBDs) have been successfully integrated in an enhancement-mode (e-mode) HEMT technology baseline. A variety of low-voltage analog/logic devices and passive components further supports the GaN ICs platform. These results significantly contribute to monolithic GaN integration for power ICs and create key opportunities for the development of GaN power circuits and complex converter topologies
