92 research outputs found
A new EDA flow for the Mitigation of SEUs in Dynamic Reconfigurable FPGAs
No full textThis work presents a new EDA flow that aims to increase the design robustness versus transient errors when the dynamic reconfigurable computing paradigm is adopted. In brief, we propose a modification of the existing commercial toolchain flow to make transient error aware designs. Aiming at that scope, a new algorithm for the design mapping has been developed reducing Single Event Upsets on the routing interactions between reconfigurable placed modules. The performance evaluation of the EDA flow has been evaluated with neutron-based radiation test experiments and fault injection using a proper dynamic reconfiguration context. Results prove a reduction of the transient error sensitivity about 3 orders of magnitude without any area overhead and with a performance degradation of less than 10% on the average
Analysis of Proton-induced Single Event Effect in the On-Chip Memory of Embedded Processor
Get PDFEmbedded processors had been established as common components in modern systems. Usually, they are provided with different types and hierarchical levels of memory, some of them integrated into the same chip (on-chip memory).
Due to the high density of transistors, memories are known to be particularly sensitive to soft errors. Soft errors afflicting
memories can manifest in various forms besides traditional single-bit value corruption. In this paper, a comprehensive
description of radiation-induced effects detected in the SRAM on-chip memory of an ARM Cortex-A9 MPCore during a
proton-beam test is performed. The experimental setup, data acquisition methodology, and observed effects are reported in detail including a cross-section for different energies. Fault models for system-level reliability evaluation are proposed,
complete with their distribution. Finally, the proposed fault models are used in fault injection campaigns on a software
benchmark suite and results are discussed
SETA: A CAD tool for Single Event Transient Analysis and Mitigation on Flash-based FPGAs
Get PDFFlash-based Field Programmable Gate Array (FPGA) devices are nowadays golden cores of many applications especially in space and avionic fields where reliability is becoming an important concern. In particular, for Flash-based FPGAs when adopted in those applications, the main concern is radiation-induced voltage glitched know as Single Event Transient (SET) in the combinational logic. In this work, a new CAD tool has been developed in order to evaluate the sensitivity of the implemented circuit regarding SET and to mitigate their effects. The proposed tool has been applied to an industrial design adopted by the EUCLID space mission including more than ten different modules. The experimental results demonstrated the feasibility and efficiency of proposed tool
Validation of a tool for estimating the effects of Soft- Errors on modern SRAM-based FPGAs
No full textPredicting soft errors on SRAM-based FPGAs without a wasteful time-consuming or a high-cost has always been a very difficult goal. Among the available methods, we proposed an updated version of analytical approach to predict Single Event Effects (SEEs) based on the analysis of the circuit the FPGA implements. In this paper, we provide an experimental validation of this approach, by comparing the results it provides with a fault injection campaign. We adopted our analytical method for computing the error-rate of a design implemented on SRAM-based FPGA. Furthermore, we compared the obtained soft-error figure with the one measured by fault injection. Experimental analysis demonstrated the analytical method closely match the effective soft-error rates becoming a viable solution for the soft-error estimation at early design phase
Analysis of radiation-induced SEUs on dynamic reconfigurable systems
No full textSRAM-Based FPGAs are widely employed in space and avionics computing. The unfriendly environment and FPGA radiation sensibility can have dramatic drawbacks on the application reliability. The partial self-reconfiguration ability gives an excellent aid to counteract single event upsets (SEUs) caused by excessive silicon ionization, and the consequent system misbehavior. Related to this feature, fault injection and fault emulation and configuration scrubbing, has been carried out over three versions of a reconfigurable Fast Fourier Transform (FFT) system: a single FFT, a single larger FFT and a FFT with TMR architecture. The analysis has been focused on multiple injected SEUs scenario, considering the availability problem in a real-time application and highlighting the circuit tolerance at the upset presence. This operation has the goal to emulate as much as possible a real radiation test avoiding all the handicaps that this procedure involves. The obtained results have shown the advantages of the configuration scrubbing performed with the aim to fix multiple upsets, achieving up to 13.6% of circuit hardening. The achieved conclusions are an interesting starting point for the study of fault mitigation techniques through the use of reconfiguration. The projects have been tested on a Z-7010 AP So
A Reliable Fault Classifier for Dependable Systems on SRAM-based FPGAs
No full textThis paper presents an algorithm for the discrimination of faults in FPGAs based on their recovery possibility; some faults can be recovered by reconfiguring the faulty part of the device, others have a destructive effect. After classification has been carried out, the suitable fault recovery strategy is applied, with the final aim of enabling the exploitation of FPGAs, in particular SRAM-based ones, for critical applications, such as the ones in the space environment. In this scenario, we investigate the reliable implementation of the fault classification algorithm, that can be so integrated in an overall reliable system
Smart behavioral netlist simulation for SEU protection verification
No full textSchulz S, Beltrame G, Merodio-Codinachs D. Smart behavioral netlist simulation for SEU protection verification. Esa Sp. 2008:406-411.This paper presents a novel approach to verify the correct implementation of Triple Modular Redundancy (TMR) for the memory elements of a given netlist using formal analysis. The purpose is detecting any issues that might incur during the use of automatic tools for TMR insertion, optimization, place and route, etc. Our analysis does not require a testbench and can perform full, exhaustive coverage within less than an hour even for large designs. This is achieved by applying a divide et impera approach, splitting the circuit into smaller submodules without loss of generality, instead of applying formal verification to the whole netlist at once. The methodology has been applied to a production netlist of the LEON2-FT processor that reported errors during radiation testing, successfully showing its TMR implementation issues
Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs
No full textDue to the decreasing feature sizes of VLSI circuits, radiation induced Single Event Transients (SETs) are increasingly dominating the event ratio on modern VLSI devices. In particular, Flash-based FPGAs are characterized by the main concern of radiation-induced voltage glitches or SETs in the combinational logic. Transient pulses can be sampled by a storage element and can propagate through the circuit up to the outputs and leading to an error. In this paper, we propose a complete implementation flow including sensitivity analysis, fault tolerant mapping and fault tolerance-oriented place and route for the effective design of SET tolerant circuits on Flash-based FPGAs. In details, the proposed method allows accurate measurement of the transient pulse source induced by radiation particles and estimation of the SET error rate on the overall circuit. Besides the developed method provides a netlist mapping and place and route tool for the selective mitigation of SET effects. The proposed method has been applied to an industrial design oriented to the Euclid European Space Agency mission including more than ten different modules. The obtained results show an improvement of the total filtering capability of around 43 times with respect to the original netlist without affecting the timing constraints of the circuit
Exploring the Impact of Soft Errors on the Reliability of Real-Time Embedded Operating Systems
Get PDFThe continuous scaling of electronic components has led to the development of high-performance microprocessors that are suitable even for safety-critical applications where radiation-induced errors such as Single Event Effects (SEEs) can have a significant impact on the performance and reliability of the system. This work is dedicated to investigating the reliability of systems based on programmable hardware and Real-time operating Systems (RTOS) in the presence of architectural faults induced by soft errors in the configuration memory of the programmable hardware. We performed a proton radiation test campaigned at PSI radiation facility to identify the fault model affecting the configuration memory of Xilinx Zynq-7020 reconfigurable AP-Soc Device. The identified fault model in terms of SEU and MBU clusters has been used to evaluate the impact of proton-induced faults on applications running within FreeRTOS on a Microblaze soft processor. A Single Event Multiple Upset fault model resulting from a proton test is presented, focusing on characteristics such as shape, size, and frequency of observed cluster of errors. We conduct two fault injection campaigns and analyze the results to assess the effect of cluster size on system reliability. Moreover, we discuss software exceptions caused by faults that can affect the hardware structure of the soft processor
PyXEL: Exploring Bitstream Analysis to Assess and Enhance the Robustness of Designs on FPGAs
Get PDFCommercial hardware-reconfigurable systems-on-chip are highly attractive for mission-critical applications in the space and automotive industries. However, their vulnerability to soft errors is a major concern, and analyzing the robustness of these systems is a complex task due to the lack of dedicated tools, information, and methodologies available. PyXEL is a tool designed to address these issues, providing the methodology for automating reliability analysis based on radiation and fault injection campaigns and facilitating the development of mitigation solutions based on customized place-and-route. Furthermore, PyXEL offers the methodology for visualizing, decoding, and analyzing the configuration data of programmable hardware devices, enabling more precise and efficient evaluation and analysis of the robustness of systems implemented on programmable hardware devices
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